Details, datasheet, quote on part number: CDCM7005
PartCDCM7005
CategorySemiconductors => Clock and Timing => Clock Jitter Cleaners => Single-Loop PLL
Part familyCDCM7005 High Performance, Low Phase Noise, Low Skew Clock Synchronizer that Synchronizes Ref Clock to VCXO
DescriptionHigh Performance, Low Phase Noise, Low Skew Clock Synchronizer that Synchronizes Ref Clock to VCXO 48-VQFN -40 to 85
CompanyTexas Instruments, Inc.
StatusACTIVE
ROHSY
SampleNo
DatasheetDownload CDCM7005 datasheet
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Specifications 
Output Frequency(Min)(MHz)0
Input LevelLVCMOS (REF_CLK),LVPECL (VCXO_CLK)
Number of Inputs2
Operating Temperature Range(C)-40 to 85
Package GroupBGA,VQFN
RatingCatalog
Approx. Price (US$)9.50 | 1ku
Supply Voltage(Min)(V)3
Supply Voltage(Max)(V)3.6
Number of Outputs5
Output Frequency(Max)(MHz)1500
Divider Ratio1 to 16
Output LevelLVCMOS,LVPECL
FeaturesProgrammable Delay
  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
48RGZVQFNS-PQFP-N2500LARGE T&RCDCM7005 77.9.5
Application notes
• Phase Noise/Phase Jitter Performance of CDCM7005
Phase Noise/Phase Jitter Performance of CDCM7005 | Doc
• TLK313x/CDCM7005 Multi-hop Performance | Doc
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Features, Applications

3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER
FEATURES

High Performance LVPECL and LVCMOS PLL Clock Synchronizer Two Reference Clock Inputs (Primary and Secondary Clock) for Redundancy Support With Manual or Automatic Selection Accepts LVCMOS Input Frequencies to 200 MHz VCXO_IN Clock is Synchronized to One of the Two Reference Clocks VCXO_IN Frequencies to 2.2 GHz (LVPECL) Outputs Can Be a Combination of LVPECL and LVCMOS (Up to Five Differential LVPECL Outputs to 10 LVCMOS Outputs) Output Frequency is Selectable x1, on Each Output Individually Efficient Jitter Cleaning From Low PLL Loop Bandwidth Low Phase Noise PLL Core Programmable Phase Offset (PRI_REF and SEC_REF to Outputs) Wide Charge Pump Current Range From 3 mA Dedicated Charge Pump Supply (VCC_CP) for Wide Tuning Voltage Range VCOs Presets Charge Pump to VCC_CP/2 for Fast Center-Frequency Setting of VC(X)O Analog and Digital PLL Lock Indication Provides VBB Bias Voltage Output for Single-Ended Input Signals (VCXO_IN) Frequency Hold-Over Mode Improves Fail-Safe Operation Power-Up Control Forces LVPECL Outputs 3-State at VCC 1.5 V SPI Controllable Device Setting 3.3-V Power Supply Packaged in 64-Pin BGA (0,8 mm Pitch ­ ZVA) or 48-Pin QFN (RGZ) Industrial Temperature Range to 85°C

PRI_REF REF_SEL VCC_CP CP_OUT CTRL_LE CTRL_CLK



Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

DESCRIPTION

The is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O: VC(X)O_IN / PRI_REF / M or VC(X)O_IN / SEC_REF / M VC(X)O_IN clock operates to 2.2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements. The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005 are user definable and can be any combination up to five LVPECL outputs to 10 LVCMOS outputs. The LVCMOS outputs are arranged in pairs Y1A:Y1B,...), so that each pair has the same frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure that all outputs are synchronized for low output skew. All device settings, like outputs signaling, divider value, input selection, and many more, are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings. The device operates in 3.3-V environment and is characterized for operation from to 85°C.

PRI_REF R EF_MUX LVCMOS SEC_REF Progr. Delay M Progr. Divider M 2
÷3 LV CMOS ÷4 VCXO_IN PECL INPUT Y2_MUX LV PECL Y2B LV CMOS Y2A

 

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