|Title||32-BIT ARM CORTEX-M0+|
The LPC84x from NXP Semiconductors is an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz, supporting up to 64 KB of Flash memory and 16 KB of SRAM. The LPC84x family features exceptional power efficiency with down to 90 µA/MHz (active) in low-current mode using the free running oscillator (FRO) as the clock source. The peripheral complement of the LPC84x includes a CRC engine, four I2C bus interfaces, up to five USARTs, up to two SPI interfaces, capacitive touch interface, one multi-rate timer, self-wake-up timer, SCTimer/PWM, one general purpose 32-bit counter/timer, a DMA, one 12-bit ADC, two 10-bit DACs, one analog comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine, and up to 54 general-purpose I/O pins.
|Datasheet||Download LPC844M201JBD64E datasheet
|Others parts numbering|
32-bit ARM Cortex-M0+ microcontroller; 64 KB flash and 16 KB SRAM; FAIM memory; 12-bit ADC; 10-bit DACs; Comparator; Capacitive Touch Interface
The LPC84x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies to 30 MHz. The LPC84x support KB of flash memory and KB of SRAM. The peripheral complement of the LPC84x includes a CRC engine, four I2C-bus interfaces, up to five USARTs, up to two SPI interfaces, Capacitive Touch Interface, one multi-rate timer, self-wake-up timer, SCTimer/PWM, one general purpose 32-bit counter/timer, a DMA, one 12-bit ADC, two 10-bit DACs, one analog comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine, and to 54 general-purpose I/O pins. For additional documentation related to the LPC84x parts, see Section 18.
System: ARM Cortex-M0+ processor (revision r0p1), running at frequencies to 30 MHz with single-cycle multiplier and fast single-cycle I/O port. ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC). System tick timer. AHB multilayer matrix. Serial Wire Debug (SWD) with four break points and two watch points. JTAG boundary scan (BSDL) supported. Micro Trace Buffer (MTB). Memory: 64 KB on-chip flash programming memory with 64 Byte page write and erase. Fast Initialization Memory (FAIM) allowing the user to configure chip behavior on power-up. Code Read Protection (CRP) 16 KB SRAM consisting of two 8 KB contiguous SRAM banks. One KB of SRAM can be used for MTB. Bit-band addressing supported to permit atomic operations to modify a single bit. ROM API support: Boot loader. Supports Flash In-Application Programming (IAP).
Supports In-System Programming (ISP) through USART, SPI, and I2C. FAIM API. FRO API. On-chip ROM APIs for integer divide. Digital peripherals: High-speed GPIO interface connected to the ARM Cortex-M0+ I/O bus with to 54 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, programmable open-drain mode, input inverter, and digital filter. GPIO direction control supports independent set/clear/toggle of individual bits. High-current source output driver (20 mA) on four pins. High-current sink driver (20 mA) on two true open-drain pins. GPIO interrupt generation capability with boolean pattern-matching feature on eight GPIO inputs. Switch matrix for flexible configuration of each I/O pin function. CRC engine. DMA with 25 channels and 13 trigger inputs. Capacitive Touch Interface. Timers: One SCTimer/PWM with five input and seven output functions (including capture and match) for timing and PWM applications. Inputs and outputs can be routed to or from external pins and internally to or from selected peripherals. Internally, the SCTimer/PWM supports 8 match/captures, 8 events, and 8 states. One 32-bit general purpose counter/timer, with four match outputs and three capture inputs. Supports PWM mode, external count, and DMA. Four channel Multi-Rate Timer (MRT) for repetitive interrupt generation up to four programmable, fixed rates. Self-Wake-up Timer (WKT) clocked from either Free Running Oscillator (FRO), a low-power, low-frequency internal oscillator, or an external clock input in the always-on power domain. Windowed Watchdog timer (WWDT). Analog peripherals: One 12-bit ADC with to 12 input channels with multiple internal and external trigger inputs and with sample rates to 1.2 Msamples/s. The ADC supports two independent conversion sequences. Comparator with five input pins and external or internal reference voltage. Two 10-bit DACs. Serial peripherals: Five USART interfaces with pin functions assigned through the switch matrix and two fractional baud rate generators. Two SPI controllers with pin functions assigned through the switch matrix. Four I2C-bus interfaces. One I2C supports Fast-mode Plus with 1 Mbit/s data rates on two true open-drain pins and listen mode. Three I2Cs support data rates to 400 kbit/s on standard digital pins. Clock generation:All information provided in this document is subject to legal disclaimers.
Free Running Oscillator (FRO). This oscillator provides a selectable 18 MHz, 24 MHz, and 30 MHz outputs that can be used as a system clock. Also, these outputs can be divided down to 1.125 MHz, 1.5 MHz, 1.875 MHz, 9 MHz, 12 MHz, and 15 MHz for system clock. The FRO is trimmed 1 % accuracy over the entire voltage and temperature range 70 C. Low power boot at 1.5 MHz using FAIM memory. External clock input for clock frequencies to 25 MHz. Crystal oscillator with an operating range of 1 MHz to 25 MHz. Low power oscillator can be used as a clock source to the watchdog timer. Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz. PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator, the external clock input, or the internal FRO. Clock output function with divider that can reflect all internal clock sources. Power control: Reduced power modes: sleep mode, deep-sleep mode, power-down mode, and deep power-down mode. Wake-up from deep-sleep and power-down modes on activity on USART, SPI, and I2C peripherals. Timer-controlled self wake-up from deep power-down mode. Power-On Reset (POR). Brownout detect (BOD). Unique device serial number for identification. Single power supply to 3.6 V). Operating temperature range to +105 °C. Available LQFP48, HVQFN48, and HVQFN33 packages.
Sensor gateways Industrial Gaming controllers 8/16-bit applications Consumer Climate control Simple motor control Portables and wearables Lighting Motor control Fire and security applications
|Some Part number from the same manufacture NXP Semiconductors|
The LPC84x from NXP Semiconductors is an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz, supporting up to 64 KB of Flash memory and 16 KB of SRAM. The LPC84x