Details, datasheet, quote on part number: AS7C3256
CategoryMemory => SRAM => Async. SRAM => 256 Kb
Description3.3V Fast Asynchronous, 256K, 32Kx8
CompanyAlliance Semiconductor
DatasheetDownload AS7C3256 datasheet
Cross ref.Similar parts: CY7C1399B-12VC, CY7C1399B-12VCT, IS61LV256
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Features, Applications

AS7C256 (5V version) AS7C3256 (3.3V version) Industrial and commercial temperature Organization: 32,768 words 8 bits High speed

12/15/20 ns address access time ns output enable access time

Easy memory expansion with CE and OE inputs TTL-compatible, three-state I/O 28-pin JEDEC standard packages

Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current AS7C256 AS7C3256

The a 5V/3.3V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 32,768 words 8 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance's advanced circuit design and process techniques permit 3.3V operation without sacrificing performance or operating margins. The device enters standby mode when CE is high. CMOS standby mode consumes 3.6 mW. Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Equal address access and cycle times (tAA, tRC, tWC) 12/15/20 ns with output enable access times (tOE) 8 ns are ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible and 5V tolerant. Operation is from a single 3.30.3V supply. The AS7C(3)256A is packaged in high volume industry standard packages.

Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied DC current into outputs (low) Device AS7C256 AS7C3256 Symbol Vt2 PD Tstg Tbias IOUT Min Max +7.0 +5.0 VCC Unit

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

WE OE Data High Z High Z DOUT DIN Mode Standby (ISB, ISB1) Output disable (ICC) Read (ICC) Write (ICC)

Parameter Supply voltage Device AS7C3256 AS7C256 Input voltage AS7C3256 Ambient operating temperature

-12 Parameter Input leakage current Sym Test conditions |ILI| VCC = Max, Vin = GND to VCC Device Both

Output leakage V = Max, |ILO| CC current VOUT = GND to VCC Operating power supply current ICC VCC = Max, CE VIL f = fMax, IOUT = 0mA VCC = Max, CE VIL f = fMax, IOUT = 0mA

Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CE, WE, OE I/O Test conditions Vin = 0V Vin = Vout = 0V Max 5 7 Unit pF


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