Details, datasheet, quote on part number: AS7C33128NTD32A
CompanyAlliance Semiconductor
DatasheetDownload AS7C33128NTD32A datasheet


Features, Applications


Organization: 131,072 words or 36 bits NTDTM1 architecture for efficient bus operation Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3.5/4.0/5.0 ns Fast OE access time: 3.5/4.0/5.0 ns Fully synchronous operation Flow-through or pipelined mode Asynchronous output enable control

Economical 100-pin TQFP package Byte write enables Clock enable for operation hold Multiple chip enables for easy expansion 3.3V core power supply or 3.3V I/O operation with separate VDDQ 30 mW typical standby power Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation


-166 Minimum cycle time Maximum pipelined clock frequency Maximum pipelined clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) Units ns MHz ns mA

The AS7C33128NTD36A family is a high performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) device organized as 131,072 words or 36 bits that incorporates a LATE Write. This variation of the 4Mb sychronous SRAM uses the No Turnaround Delay (NTD) architecture, featuring an enhanced write operation that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address are all applied to the device on the same clock edge. If a read command follows this write command, the system must wait for two dead cycles for valid data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-write operations. NTD devices use the memory bus more efficiently by introducing a write latency that matches the two-cycle pipelined or one-cycle flowthrough read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTD, write and read operations can be used in any order without producing dead bus cycles. Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 32/36 bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations. It can be tied low for normal operations. Outputs to a high impedance state when the device is deselected by any of the three chip enable inputs. (Refer to synchronous truth table on page 4.) In pipelined mode, a two-cycle deselect latency allows pending read or write operations to be completed. Use the ADV/LD (burst advance) input to perform burst read, write, and deselect operations. When ADV/LD is high, external addresses, chip select, and R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including burst, can be stalled using the clock enable input, CEN = 1. The AS7C33128NTD36A and AS7C33128NTD32A operate with 5% power supply for the device core (VDD). DQ circuits use a separate power supply (VDDQ) that operates across or 2.5V ranges. These devices are available 1420 mm TQFP package.

Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals Address and control pins I/O pins Test conditions Vin = 0V Vin = Vout 5 7 Max Unit pF

Signal CLK CEN A0, A1 DQ[a,b,c,d] CE1, CE2 ADV/LD R/W BW[a,b,c,d] OE LBO ZZ NC I/O Properties Description I I/O CLOCK SYNC ASYNC STATIC ASYNC Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock. Clock enable. When de-asserted high, the clock input signal is masked. Address. Sampled when all chip enables are active and ADV/LD is asserted. Data. Driven as output when the chip is enabled and OE is active. Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are ignored when ADV/LD is high. Advance or Load. When sampled high, the internal burst address counter will increment in the order defined by the LBO input value. (refer to table on page 2) When low, a new address is loaded. A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE operation. Is ignored when ADV/LD is high. Byte write enables. Used to control write on individual bytes. Sampled along with WRITE command and BURST WRITE. Asynchronous output enable. I/O pins are not driven when OE is inactive. Count mode. When driven high, count sequence follows Intel XOR convention. When driven low, count sequence follows linear convention. This input should be static when the device is in operation. Flow-through mode.When low, enables single register flow-through mode. Connect to VDD if unused or for pipelined operation. Snooze. Places device in low power mode. Data is retained. Connect to VSS if unused. No connects. Note that pin & 84 will be used for future address expansion Mb and16Mb density.

Parameter Power supply voltage relative to VSS Input voltage relative to VSS (input pins) Input voltage relative to VSS (I/O pins) Power dissipation DC output current Storage temperature (plastic) Temperature under bias (Junction) Symbol VDD, VDDQ VIN PD IOUT Tstg Tbias Min Max +4.6 VDD + 0.5 VDDQ Unit mA

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.


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