|Category||Memory => SRAM => Sync. SRAM => 2 Mb|
|Description||3.3V Synchronous, 2M, 128Kx16|
|Datasheet||Download AS7C33128PFS16A datasheet
Organization: or 18 bits Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3.5/4.0/5.0 ns Fast OE access time: 3.5/4.0/5.0 ns Fully synchronous register-to-register operation Flow-through mode Single-cycle deselect Asynchronous output enable control Economical 100-pin TQFP package Byte write enables Multiple chip enables for easy expansion 3.3V core power supply or 3.3V I/O operation with separate VDDQ 30 mW typical standby power in power-down modeNC VDDQ VSSQ NC DQb VSSQ VDDQ DQb FT VDD NC VSS DQb VDDQ VSSQ DQb DQpb/NC NC VSSQ VDDQ NC
Byte Write registers Byte Write registers
≠166 Minimum cycle time Maximum pipelined clock frequency Maximum pipelined clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) Units ns MHz ns mAA16 NC VDDQ VSSQ NC DQpa/NC DQa VSSQ VDDQ DQa VSS NC VDD ZZ DQa VDDQ VSSQ DQa NC VSSQ VDDQ NC
The AS7C33128PFS16A and AS7C33128PFS18A are high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM) devices organized or 18 bits and incorporate a pipeline for highest frequency on any given technology. Fast cycle times 6.0/7.5/10 ns with clock access times (tCD) 3.5/4.0/5.0 ns enable 166, 133, and 100 MHz bus frequencies. Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses. Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register. When ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, is carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but it is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved count sequence. With LBO driven low, the device uses a linear count sequence. Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 16/ 18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signal(s). BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when BWn is sampled low regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented internally to the next burst address if BWn and ADV are sampled low. Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow. ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC. WE signals are sampled on the clock edge that samples ADSC low (and ADSP high). Master chip select CE0 blocks ADSP, but not ADSC. The AS7C33128PFS16A and AS7C33128PFS18A operate from a 3.3V supply. I/Os use a separate power supply that can operate or 3.3V. These devices are available 14◊20 mm TQFP packaging.
Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals Address and control pins I/O pins Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 Unit pFWrite enable truth table (per byte)
Key: X = don't care. L = low. H = high. T = true. F = false. * = valid read. WE or WEn = internal write signal.
Signal CLK A0≠A16 DQ[a,b] CE1, CE2 ADSP ADSC ADV GWE BWE BW[a,b] OE LBO I/O I I/O Properties CLOCK SYNC ASYNC STATIC default = high STATIC ASYNC Description Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock. Address. Sampled when all chip enables are active and ADSC or ADSP are asserted. Data. Driven as output when the chip is enabled and OE is active. Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information. Synchronous chip enables. Active high and active low, respectively. Sampled on clock edges when ADSC is active or when CE0 and ADSP are active. Address strobe (processor). Asserted low to load a new address or to enter standby mode. Address strobe (controller). Asserted low to load a new address or to enter standby mode. Burst advance. Asserted low to continue burst read/write. Global write enable. Asserted low to write all 16/18 bits. When high, BWE and BW[a,b] control write enable. Byte write enable. Asserted low with GWE = high to enable effect of BW[a,b] inputs. Write enables. Used to control write of individual bytes when GWE = high and BWE = low. If any of BW[a,b] is active with GWE = high and BWE = low the cycle is a write cycle. If all BW[a,b] are inactive, the cycle is a read cycle. Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read mode. Count mode. When driven high, count sequence follows Intel XOR convention. When driven low, count sequence follows linear convention. This signal is internally pulled high. Flow-through mode.When low, enables single register flow-through mode. Connect to VDD if unused or for pipelined operation. Sleep. Places device in low power mode. Data is retained. Connect to GND if unused.
Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation DC output current Storage temperature (plastic) Temperature under bias Symbol VDD, VDDQ VIN PD IOUT Tstg Tbias Min Max +4.6 VDD + 0.5 VDDQ Unit mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.
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