Details, datasheet, quote on part number: AS7C331MNTD18A-200BI
CategoryMemory => SRAM => Sync. SRAM => 16 Mb
Description3.3V NTD TM Synchronous SRAM, 18M, 1Mx18
CompanyAlliance Semiconductor
DatasheetDownload AS7C331MNTD18A-200BI datasheet


Features, Applications

Organization: 1,048,576 words 18 bits NTDTM1 architecture for efficient bus operation Fast clock speeds to 200 MHz in LVTTL/LVCMOS Fast clock to data access: 3/3.4/3.8 ns Fast OE access time: 3/3.4/3.8 ns Fully synchronous operation Flow-through or pipelined mode Asynchronous output enable control

Available in 100-pin TQFP and 165-ball BGA package Byte write enables Clock enable for operation hold Multiple chip enables for easy expansion 3.3V core power supply or 3.3V I/O operation with separate VDDQ Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation

-200 Minimum cycle time Maximum pipelined clock frequency Maximum pipelined clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC)

1 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

The AS7C331MNTD18A family is a high performance CMOS 16 Mbit synchronous Static Random Access Memory (SRAM) organized as 1,048,576 words 18 bits and incorporates a LATE Write. This variation of the 16Mb+ synchronous SRAM uses the No Turnaround Delay (NTDTM) architecture, featuring an enhanced write operation that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address are all applied to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modifywrite operations. NTDTM devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle flowthrough read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTDTM, write and read operations can be used in any order without producing dead bus cycles. Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 18 bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for normal operations. Outputs to a high impedance state when the device is de-selected by any of the three chip enable inputs. In pipelined mode, a two cycle deselect latency allows pending read or write operations to be completed. Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including burst, can be stalled using the CEN=1, the clock enable input. The AS7C331MNTD18A operates with 5% power supply for the device core (VDD). DQ circuits use a separate power supply (VDDQ) that operates across or 2.5V ranges. These devices are available a 100-pin TQFP package and 165 BGA Ball Grid Array package.

Parameter Input capacitance I/O capacitance Symbol CIN CI/O I/O pins Signals Address and control pins Test conditions Vin = 0V Vin = Vout = 0V Max 5 7 Unit pF


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