|Datasheet||Download AME8500AEEVBE18 datasheet
The AME8500 family allows the user to customize the CPU reset function without any external components. The user has a large choice of reset voltage thresholds, reset time intervals, and output driver configurations, all of which are preset at the factory. Each wafer is trimmed to the customer's specifications. These circuits monitor the power supply voltage of µP based systems. When the power supply voltage drops below the voltage threshold a reset is asserted immediately (within an interval TD1). The reset remains asserted after the supply voltage rises above the voltage threshold for a time interval, TD2. The reset output may be either active high (RESET) or active low (RESETB). The reset output may be configured as either push/pull or open drain. The state of the reset output is guaranteed to be correct for supply voltages greater than 1V. The AME8501 includes all the above functionality plus an overtemperature shutdown function. When the ambient temperature exceeds 80oC a reset is asserted and remains asserted until the temperature falls below 60oC. Space saving SOT23 packages and micropower quiescent current (<3.0µA) make this family a natural for portable battery powered equipment.Note: * External pull-up resistor is required if opendrain output is used. k is recommended.
l Small packages: l 11 voltage threshold options l Tight voltage threshold tolerance l 5 reset interval options l 4 output configuration options l Wide temperature range 85oC l Low temperature coefficient 100ppm/oC(max) l Low quiescent current 3.0µA l Thermal shutdown option (AME8501)
Portable electronics Power supplies Computer peripherals Data acquisition systems Applications using CPUs Consumer electronics
GND RESETB/RESET Ground This pin can be ordered as RESET or RESETB. RESET is active high. RESETB is active low. It is also available with an open drain or pushpull output. Positive power supply. A reset is asserted after this voltage drops below a predetermined level. After V DD rises above that level the reset output remains asserted until the end of the reset timeout period.
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