|Description||250 Ksps, 10-Bit ADC in 6 Lead SC70|
|Datasheet||Download AD7910 datasheet
FEATURES Throughput Rate: 250 kSPS Specified for VDD 5.25 V Low Power: 3.6 mW Typ at 250 kSPS with 3 V Supplies 12.5 mW Typ at 250 kSPS with 5 V Supplies Wide Input Bandwidth: 71 dB SNR at 100 kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface SPITM/QSPITM/MICROWIRETM/DSP Compatible Standby Mode: 1 A Max 6-Lead SC70 Package 8-Lead MSOP Package APPLICATIONS Battery-Powered Systems Personal Digital Assistants Medical Instruments Mobile Communications Instrumentation and Control Systems Data Acquisition Systems High Speed Modems Optical Sensors FUNCTIONAL BLOCK DIAGRAM
The reference for the part is taken internally from VDD. This allows the widest dynamic input range to the ADC. Thus the analog input range for the part 0 to VDD. The conversion rate is determined by the SCLK.
2. Low Power Consumption. 3. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power consumption to be reduced when Power-Down mode is used while not converting. The part also features a Power-Down mode to maximize power efficiency at lower throughput rates. Current consumption 1 A max and 50 nA typically when in Power-Down mode. 4. Reference derived from the power supply. 5. No Pipeline Delay. The parts feature a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control.
The AD7910/AD7920 are respectively 10-bit and 12-bit, high speed, low power, successive approximation ADCs. The parts operate from a single 5.25 V power supply and feature throughput rates to 250 kSPS. The parts contain a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 13 MHz. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. There are no pipeline delays associated with the part. The AD7910/AD7920 use advanced design techniques to achieve very low power dissipation at high throughput rates.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: © 2002 Analog Devices, Inc. All rights reserved.5 MHz, fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless
Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD)3 Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Intermodulation Distortion (IMD)3 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error3, 4 Gain Error3, 4 Total Unadjusted Error (TUE)3, 4 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN5 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance5 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time3 Throughput Rate POWER REQUIREMENTS VDD IDD Normal Mode(Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation6 Normal Mode (Operational) Full Power-Down
Digital I/Ps V or VDD 5.25 V, SCLK On or Off VDD 3.6 V, SCLK On or Off VDD 5.25 V, fSAMPLE = 250 kSPS VDD 3.6 V, fSAMPLE = 250 kSPS Typically 50 nA VDD 5 V, fSAMPLE = 250 kSPS VDD 3 V, fSAMPLE = 250 kSPS VDD 5 V VDD 3 V
NOTES 1 Temperature range from +85°C. 2 Operational from 2.0 V, with input high voltage (V INH) 1.8 V min. 3 See Terminology section. 4 SC70 values guaranteed by characterization. 5 Sample tested °C to ensure compliance. 6 See Power Versus Throughput Rate section. Specifications subject to change without notice.
Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Intermodulation Distortion (IMD)3 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity3 Differential Nonlinearity Offset Error3, 5 Gain Error3, 5 Total Unadjusted Error (TUE)3,5 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN6 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance6 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time3 Throughput Rate16 SCLK Cycles with SCLK at 5 MHz See Serial Interface Section
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