|Description||4-Channel 200 Ksps, 12-Bit A/D Converter With Sequencer in 16-Lead Tssop|
|Datasheet||Download AD7923 datasheet
FEATURES Fast Throughput Rate: 200 kSPS Specified for AVDD 5.25 V Low Power: 3.6 mW Max at 200 kSPS with 3 V Supply 7.5 mW Max at 200 kSPS with 5 V Supply 4 (Single-Ended) Inputs with Sequencer Wide Input Bandwidth: 70 dB Min SNR at 50 kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High Speed Serial Interface SPITM/QSPITM/ MICROWIRETM/DSP Compatible Shutdown Mode: 0.5 A Max 16-Lead TSSOP Package
The a 12-bit, high speed, low power, 4-channel, successive approximation ADC. The part operates from a single 5.25 V power supply and features throughput rates to 200 kSPS. The part contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 8 MHz. The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point. There are no pipeline delays associated with the part. The AD7923 uses advanced design techniques to achieve very low power dissipation at maximum throughput rates. At maximum throughput rates, the AD7923 consumes 1.2 mA maximum with 3 V supplies, and with 5 V supplies the current consumption 1.5 mA maximum. Through the configuration of the Control Register, the analog input range for the part can be selected V to REFIN 2 „ REFIN, with either straight binary or twos complement output coding. The AD7923 features four single-ended analog inputs with a channel sequencer to allow a preprogrammed selection of channels to be converted sequentially. The conversion time for the AD7923 is determined by the SCLK frequency, as this is also used as the master clock to control the conversion. The conversion time may be as short 800 ns with a 20 MHz SCLK.
1. High Throughput with Low Power Consumption. The AD7923 offers to 200 kSPS throughput rates. At the maximum throughput rate with 3 V supplies, the AD7923 dissipates just mW of power maximum. 2. Four Single-Ended Inputs with a Channel Sequencer. A consecutive sequence of channels, through which the ADC will cycle and convert on, can be selected. 3. Single-Supply Operation with VDRIVE Function. The AD7923 operates from a single 5.25 V supply. The VDRIVE function allows the serial interface to connect directly to either 5 V processor systems independent of AV DD. 4. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. The part also features various shutdown modes to maximize power efficiency at lower throughput rates. Current consumption 0.5 mA maximum when in full shutdown. 5. No Pipeline Delay. The part features a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once off conversion control.
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Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD)2 Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Channel-to-Channel Isolation2 Full Power Bandwidth DC ACCURACY2 Resolution Integral Nonlinearity Differential Nonlinearity V to REFIN Input Range Offset Error Offset Error Match Gain Error Gain Error Match 2 „ REFIN Input Range Positive Gain Error Positive Gain Error Match Zero Code Error Zero Code Error Match Negative Gain Error Negative Gain Error Match ANALOG INPUT Input Voltage Range DC Leakage Current Input Capacitance REFERENCE INPUT REFIN Input Voltage DC Leakage Current REFIN Input Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding(AVDD = VDRIVE 5.25 V, REFIN 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.)
Version1 to REFIN 2 „ REFIN VDRIVE 0.3 „ VDRIVE ±1 10 Unit dB min dB min dB min dB max dB max dB max dB max dB typ dB typ ns typ ps typ dB typ MHz typ MHz typ Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max V mA max pF typ V mA max kW typ V min V max mA max pF max Test Conditions/Comments fIN = 50 kHz Sine Wave, fSCLK = 20 MHz 3 V Typically 5 V Typically 3 V Typically 5 V Typically 3 V Typically = 40.1 kHz, = 41.5 kHzGuaranteed No Missed Codes to 12 Bits. Straight Binary Output Coding Typically ± 0.5 LSB
REFIN to +REFIN Biased about REFIN with Twos Complement Output Coding Typically ± 0.8 LSB
VDRIVE 0.2 V min 0.4 V max ±1 mA max 10 pF max Straight (Natural) Binary Twos Complement
Parameter CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS AVDD VDRIVE IDD4 During Conversion Normal Mode (Static) Normal Mode (Operational) fSAMPLE = 200 kSPS Using Auto Shutdown Mode fSAMPLE = 200 kSPS Auto Shutdown (Static) Full Shutdown Mode Power Dissipation4 Normal Mode (Operational) fSAMPLE = 200 kSPS Auto Shutdown (Static) Full Shutdown Mode
NOTES 1 Temperature ranges as follows: B Version: +85C. 2 See Terminology section. 3 Sample tested C to ensure compliance. 4 See Power versus Throughput Rate section. Specifications subject to change without notice.
Test Conditions/Comments 16 SCLK Cycles with SCLK at 20 MHz Sine Wave Input Full-Scale Step Input See Serial Interface Section
Digital I/Ps V or VDRIVE AVDD 5.25 V, fSCLK = 20 MHz AVDD 3.6 V, fSCLK = 20 MHz AVDD 5.25 V, SCLK On or Off AVDD 5.25 V, fSCLK = 20 MHz AVDD 3.6 V, fSCLK = 20 MHz AVDD 5.25 V, fSAMPLE = 200 kSPS AVDD 3.6 V, fSAMPLE = 200 kSPS SCLK On or Off (20 nA typ) SCLK On or Off (20 nA typ) AVDD 5 V, fSCLK = 20 MHz AVDD 3 V, fSCLK = 20 MHz AVDD 5 V AVDD 3 V AVDD 5 V AVDD 3 V
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