|Category||Data Conversion => DAC (Digital to Analog Converters) => 10-14 bit|
|Description||Dual 12bit Byte/parallel Interface Current Output DAC|
|Datasheet||Download AD7937AR datasheet
|Cross ref.||Similar parts: DAC7801|
FEATURES Two 12-Bit DACs in One Package DAC Ladder Resistance Matching: 0.5% Surface-Mount Package 4-Quadrant Multiplication Low Gain Error (3 LSB max Over Temperature) Byte Loading Structure Fast Interface Timing APPLICATIONS Automatic Test Equipment Programmable Filters Audio Applications Synchro Applications Process ControlDAC A REGISTER UPD 12 DAC A A1 IOUTA AGNDA RFBA A0 CONTROL LOGIC CS WR VREFA VREFB RFBB
The AD7937 contains two 12-bit current output DACs on one monolithic chip. A separate reference input is provided for each DAC. The dual DAC saves valuable board space, and the monolithic construction ensures excellent thermal tracking. Both DACs are guaranteed 12-bit monotonic over the full temperature range. The AD7937 has a 2-byte (eight LSBs, four MSBs) loading structure. It is designed for right-justified data format. The control signals for register loading are A0, A1, CS, WR, and UPD. Data is loaded to the input registers when CS and WR are low. To transfer this data to the DAC registers, UPD must be taken low with WR. Added features on the AD7937 include an asynchronous CLR line which is very useful in calibration routines. When this is taken low, all registers are cleared. The double buffering of the data inputs allows simultaneous update of both DACs. Also, each DAC has a separate AGND line. This increases the device versatility; for instance, one DAC may be operated with AGND biased while the other is connected in the standard configuration. The AD7937 is manufactured using the Linear Compatible CMOS (LC2MOS) process. It is speed compatible with most microprocessors and accepts TTL, 74HC, and 5 V CMOS logic level inputs.
1. DAC-to-DAC Matching Since both DACs are fabricated on the same chip, precise matching and tracking is inherent. Many applications that are not practical using two discrete DACs are now possible. Typical matching: 0.5%. 2. Small Package Size The AD7937 is packaged in a small 24-lead SOIC. 3. Wide Power Supply Tolerance The device operates 5 V VDD, with ± 10% tolerance on this nominal figure. All specifications are guaranteed over this range.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Temperature Coefficient2; Gain/Temperature Output Leakage Current IOUTA IOUTB REFERENCE INPUT Input Resistance VREFA, VREFB Input Resistance Match DIGITAL INPUTS VIH (Input High Voltage) VIL (Input Low Voltage) IIN (Input Current) +25°C TMIN to TMAX CIN (Input Capacitance)2 POWER SUPPLY VDD IDD A Version B Version Unit
(VDD V 10%, VREFA = VREFB 10 V; IOUTA = AGNDA 0 V, IOUTB = AGNDB 0 V. All MIN to TMAX unless otherwise noted.)
All grades guaranteed monotonic over temperature. Measured using RFBA, RFBB. Both DAC registers loaded with all 1s. Typical value is 1 ppm/°C. DAC A Register loaded with all 0s. DAC B Register loaded with all 0s.
These characteristics are included for Design Guidance only and are not subject to test. (VDD 5 V; VREFA = VREFB 10 V; IOUTA = AGNDA 0 V, IOUTB = AGNDB 0 V. Output Amplifiers are AD644 except where noted.)
Parameter Output Current Settling Time Digital-to-Analog Glitch lmpulse AC Feedthrough VREFA to IOUTA VREFB to IOUTB Power Supply Rejection Gain/VDD Output Capacitance COUTA COUTB COUTA COUTB Channel-to-Channel Isolation VREFA to IOUTB VREFB to IOUTA Digital Crosstalk Output Noise Voltage Density (10 Hz100 kHz) Total Harmonic Distortion 1 2.5 Unit µs max nV-s typ Test Conditions/Comments 0.01% of full-scale range. IOUT load 100 , CEXT = 13 pF. DAC output measured from falling edge of WR. Typical Value of Settling Time is 0.6 µs. Measured with VREFA = VREFB 0 V. IOUTA, IOUTB load 100 , CEXT = 13 pF. DAC registers alternately loaded with all 0s and all 1s. VREFA, VREFB 20 V p-p 10 kHz sine wave. DAC registers loaded with all 0s. VDD = VDD max VDD min. DAC A, DAC B loaded with all 0s. DAC A, DAC B loaded with all 1s.
VREFA 20 V p-p 10 kHz sine wave, VREFB 0 V. Both DACs loaded with all 1s. VREFB 20 V p-p 10 kHz sine wave, VREFA 0 V. Both DACs loaded with all 1s. Measured for a Code Transition of all 0s to all 1s. IOUTA, IOUTB load 100 , CEXT = 13 pF. Measured between RFBA and IOUTA or RFBB and IOUTB. Frequency of measurement 10 Hz100 kHz. VIN 6 V rms, 1 kHz. Both DACs loaded with all 1s.
NOTES 1 Temperature range as follows: A, B Versions: +85°C. 2 Sample tested 25°C to ensure compliance. Specifications subject to change without notice.
Test Conditions/Comments Address Valid to Write Setup Time Address Valid to Write Hold Time Data Setup Time Data Hold Time Chip Select or Update to Write Setup Time Chip Select or Update to Write Hold Time Write Pulsewidth Clear Pulsewidth
VDD to DGND. +17 V VREFA, VREFB to AGNDA, AGNDB. 25 V VRFBA, VRFBB to AGNDA, AGNDB. 25 V Digital Input Voltage to DGND. 0.3 V, VDD +0.3 V IOUTA, IOUTB to DGND. 0.3 V, VDD +0.3 V AGNDA, AGNDB to DGND. 0.3 V, VDD +0.3 V SOIC Package JA, Thermal Impedance. 72°C/W Lead Temperature (Soldering, 10 sec). 300°C IR Ref Low Peak Temperature. 220°C Operating Temperature Range Industrial (A, B Versions). to +85°C Storage Temperature. to +150°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CLR NOTES 1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM +5V. 20ns. VIH + VIL 2. TIMING MEASUREMENT REFERENCE LEVELS IS 2Package Description Small Outline Small Outline
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7937 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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