|Category||Communication => Freq/Signal Converters/Generators|
|Description||45 or 52 MBPS Clock And Data Recovery ic|
|Datasheet||Download AD800-155 datasheet
FEATURES Standard Products or STM-1 Accepts NRZ Data, No Preamble Required Recovered Clock and Retimed Data Outputs Phase-Locked Loop Type Clock Recovery--No Crystal Required Random Jitter: 20 Peak-to-Peak Pattern Jitter: Virtually Eliminated 10KH ECL Compatible Single Supply Operation: +5 V Wide Operating Temperature Range: +85 CClock Recovery and Data Retiming Phase-Locked Loop AD800/AD802*
VCO fDET RETIMING DEVICE RECOVERED CLOCK OUTPUT RETIMED DATA OUTPUT
The AD800 and AD802 employ a second order phase-locked loop architecture to perform clock recovery and data retiming on Non-Return to Zero, NRZ, data. This architecture is capable of supporting data rates between 20 Mbps and 160 Mbps. The products described here have been defined to work with standard telecommunications bit rates. 45 Mbps DS-3 and 52 Mbps STS-1 are supported by the AD800-45 and AD800-52 respectively. 155 Mbps or STM-1 are supported by the AD802-155. Unlike other PLL-based clock recovery circuits, these devices do not require a preamble or an external VCXO to lock onto input data. The circuit acquires frequency and phase lock using two control loops. The frequency acquisition control loop initially acquires the clock frequency of the input data. The phase-lock loop then acquires the phase of the input data, and ensures that the phase of the output signals track changes in the phase of the input data. The loop damping of the circuit is dependent on the value of a user selected capacitor; this defines jitter peaking performance and impacts acquisition time. The devices exhibit 0.08 dB jitter peaking, and acquire lock on random or scrambled data within × 105 bit periods when using a damping factor of 5.
During the process of acquisition the frequency detector provides a Frequency Acquisition (FRAC) signal which indicates that the device has not yet locked onto the input data. This signal is a series of pulses which occur at the points of cycle slip between the input data and the synthesized clock signal. Once the circuit has acquired frequency lock no pulses occur at the FRAC output. The inclusion of a precisely trimmed VCO in the device eliminates the need for external components for setting center frequency, and the need for trimming of those components. The VCO provides a clock output within 20% of the device center frequency in the absence of input data. The AD800 and AD802 exhibit virtually no pattern jitter, due to the performance of the patented phase detector. Total loop jitter is 20° peak-to-peak. Jitter bandwidth is dictated by mask programmable fractional loop bandwidth. The AD800, used for data rates < 90 Mbps, has been designed with a nominal loop bandwidth 0.1% of the center frequency. The AD802, used for data rates in excess of 90 Mbps, has a loop bandwidth 0.08% of center frequency. All of the devices operate with a single 5.2 V supply.
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Parameter1 Condition NOMINAL CENTER FREQUENCY OPERATING TEMPERATURE RANGE (TMIN to TMAX) TRACKING RANGE CAPTURE RANGE STATIC PHASE ERROR = +25°C, VEE V =1 tRCS (Figure 1) tSU (Figure 0.2 K Grade B Grade(VEE = VMIN to VMAX, VCC = GND, TA = TMIN to TMAX, Loop Damping Factor = 5, unless otherwise noted)
RECOVERED CLOCK SKEW SETUP TIME TRANSITIONLESS DATA RUN OUTPUT JITTER
JITTER TRANSFER Damping Factor Capacitor, = 1, Nominal = 5, Nominal = 10, Nominal Peaking = 1, Nominal = 5, Nominal = 10, Nominal Bandwidth ACQUISITION TIME = +25°C VEE 5.2 V POWER SUPPLY Voltage (VMIN to VMAX) Current INPUT VOLTAGE LEVELS Input Logic High, VIH Input Logic Low, VIH OUTPUT VOLTAGE LEVELS Output Logic High, VOH Output Logic Low, VOL INPUT CURRENT LEVELS Input Logic High, IIH Input Logic Low, IIL OUTPUT SLEW TIMES Rise Time (tR) Fall Time (tF) SYMMETRY Recovered Clock Output
NOTES 1 Refer to Glossary for parameter definition. Specifications subject to change without notice.
Supply Voltage. 6 V Input Voltage (Pin 16 or Pin 17 to VCC). VEE +300 mV Maximum Junction Temperature SOIC Package.+150°C Ceramic DIP Package. +175°C Storage Temperature Range. to +150°C Lead Temperature Range (Soldering 60 sec). +300°C ESD Rating 1000 V
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to an absolute maximum rating condition for an extended period may adversely affect device reliability.
Maximum and minimum specifications result from statistical analyses of measurements on multiple devices and multiple test systems. Typical specifications indicate mean measurements. Maximum and minimum specifications are calculated by adding or subtracting an appropriate guardband from the typical specification. Device-to-device performance variation and test system-to-test system variation contribute to each guardband.
This is the frequency that the VCO will operate at with no input signal present and the loop damping capacitor, CD, shorted.This is the range of input data rates over which the PLL will remain in lock.
Figure 1. Recovered Clock Skew and Setup (See Previous Page)
This is the range of input data rates over which the PLL can acquire lock.
Mnemonic DATAOUT VCC2 CLKOUT VEE VCC1 AVEE ASUBST CF2 CF1 AVCC VCC1 VEE DATAIN SUBST FRAC
Description Differential Retimed Data Output Differential Retimed Data Output Digital Ground Differential Recovered Clock Output Differential Recovered Clock Output Digital VEE Digital VEE Digital Ground Analog VEE Analog Substrate Loop Damping Capacitor Input Loop Damping Capacitor Input Analog Ground Digital Ground Digital VEE Differential Data Input Differential Data Input Digital Substrate Differential Frequency Acquisition Indicator Output Differential Frequency Acquisition Indicator Output
This is the steady-state phase difference, in degrees, between the recovered clock sampling edge and the optimum sampling instant, which is assumed to be halfway between the rising and falling edges of a data bit. Gate delays between the signals that define static phase error, and IC input and output signals prohibit direct measurement of static phase error.
This is a measure of the number of data transitions, from to "1" and from to "0," over many clock periods. is the ratio 1) of data transitions to clock periods.
This is the dynamic displacement of digital signal edges from their long term average positions, measured in degrees rms, or Unit Intervals (UI). Jitter on the input data can cause dynamic phase errors on the recovered clock sampling edge. Jitter on the recovered clock causes jitter on the retimed data.
This is the jitter on the retimed data, in degrees rms, due to a specific pattern or some psuedo-random input data sequence (PRN Sequence).
Jitter tolerance is a measure of the PLL's ability to track a jittery input data signal. Jitter on the input data is best thought of as phase modulation, and is usually specified in unit intervals.
Fractional Loop Bandwidth Description 20-Pin Cerdip 20-Pin Plastic SOIC 20-Pin Plastic SOIC 20-Pin Plastic SOIC 3
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