Details, datasheet, quote on part number: OP282
CategoryAnalog & Mixed-Signal Processing => Amplifiers => Operational Amplifiers => High Speed
DescriptionDual/quad Low Power, High Speed JFET Operational Amplifiers
CompanyAnalog Devices
DatasheetDownload OP282 datasheet
Cross ref.Similar parts: MAX4242, NJM62, MC33182, MC33282, MC34182, TL62, LF442, MC34001, OPA2137, TL32
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Features, Applications

FEATURES High Slew Rate: V/ s Wide Bandwidth: 4 MHz Low Supply Current: 250 A/Amplifier Low Offset Voltage: 3 mV Low Bias Current: 100 pA Fast Settling Time Common-Mode Range Includes V+ Unity Gain Stable APPLICATIONS Active Filters Fast Amplifiers Integrators Supply Current Monitoring

Dual/Quad Low Power, High Speed JFET Operational Amplifiers OP282/OP482
PIN CONNECTIONS 8-Lead Narrow-Body SOIC 8-Lead Epoxy DIP (S Suffix) (P Suffix)

The OP282/OP482 dual and quad operational amplifiers feature excellent speed at exceptionally low supply currents. Slew rate exceeds 7 V/s with supply current under 250 A per amplifier. These unity gain stable amplifiers have a typical gain bandwidth of 4 MHz. The JFET input stage of the OP282/OP482 insures bias current is typically a few picoamps and below 500 pA over the full temperature range. Offset voltage is under 3 mV for the dual and under 4 mV for the quad. With a wide output swing, within 1.5 volts of each supply, low power consumption and high slew rate, the OP282/OP482 are ideal for battery-powered systems or power restricted applications. An input common-mode range that includes the positive supply makes the OP282/OP482 an excellent choice for highside signal conditioning. The OP282/OP482 are specified over the extended industrial temperature range. Both dual and quad amplifiers are available in plastic and ceramic DIP plus SOIC surface mount packages.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Parameter INPUT CHARACTERISTICS Offset Voltage Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift OUTPUT CHARACTERISTICS Output Voltage Swing Short Circuit Limit Open-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier Supply Voltage Range DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density

NOTE 1 The input bias and offset currents are tested = +85 C. Bias and offset currents are guaranteed but not tested at 40 C. Specifications subject to change without notice.

WAFER TEST LIMITS = +25C unless otherwise noted)

Parameter Offset Voltage Offset Voltage Input Bias Current Input Offset Current Input Voltage Range 1 Common-Mode Rejection Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Range Supply Current/Amplifier

NOTES Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. 1 Guaranteed by CMR test. Specifications subject to change without notice.

Supply Voltage. 18 V Input 18 V Differential Input 36 V Output Short-Circuit Duration. Indefinite Storage Temperature Range P, S Packages. to +150C Operating Temperature Range to +85C Junction Temperature Range P, S Packages. to +125C Lead Temperature Range (Soldering, 60 sec). +300C Package Type 8-Pin Plastic DIP (P) 8-Pin SOIC (S) 14-Pin Plastic DIP (P) 14-Pin SOIC (S) JA2 JC Units C/W

NOTES 1 For supply voltages less than 18 V, the absolute maximum input voltage is equal to the supply voltage. JA is specified for the worst case conditions, i.e., JA is specified for device in socket for cerdip, P-DIP; JA is specified for device soldered in circuit board for SOIC package.

ORDERING GUIDE Model OP482GP OP482GS Temperature Range to +85C Package Description 8-Pin Plastic DIP 8-Pin SOIC 14-Pin Plastic DIP 14-Pin SOIC Package Option N-14 SO-14


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