|Category||Analog & Mixed-Signal Processing => Amplifiers => Sample & Hold|
|Description||CMOS Quad Sample-and-hold Amplifier|
|Datasheet||Download SMP04EQ datasheet
FEATURES Four Independent Sample-and-Holds Internal Hold Capacitors High Accuracy: 12 Bit Very Low Droop Rate: 2 mV/s typ Output Buffers Stable for 500 pF TTL/CMOS Compatible Logic Inputs Single or Dual Supply Applications Monolithic Low Power CMOS Design APPLICATIONS Signal Processing Systems Multichannel Data Acquisition Systems Automatic Test Equipment Medical and Analytical Instrumentation Event Analysis DAC Deglitching
The is a monolithic quad sample-and-hold; it has four internal precision buffer amplifiers and internal hold capacitors. It is manufactured in ADI's advanced oxide isolated CMOS technology to obtain the high accuracy, low droop rate and fast acquisition time required by data acquisition and signal processing systems. The device can acquire an 8-bit input signal ± 1/2 LSB in less than four microseconds. The SMP04 can operate from single or dual power supplies with TTL/CMOS logic compatibility. Its output swing includes the negative supply. The SMP04 is ideally suited for a wide variety of sample-andhold applications, including amplifier offset or VCA gain adjustments. One or more can be used with single or multiple DACs to provide multiple setpoints within a system.
The SMP04 offers significant cost and size reduction over equivalent module or discrete designs. It is available a 16-lead hermetic or plastic DIP and surface mount SOIC packages. It is specified over the extended industrial temperature range to +85°C.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998
VDD +12.0 V, VSS = DGND = No Load, TA = Operating Temperature Range specified in Absolute Maximum Ratings, unless otherwise noted.)
Parameter Linearity Error Buffer Offset Voltage Hold Step Droop Rate Output Source Current 1 Output Sink Current1 Output Voltage Range LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Input Current DYNAMIC PERFORMANCE Acquisition Time3 Acquisition Time3 Hold Mode Settling Time Slew Rate4 Capacitive Load Stability Analog Crosstalk SUPPLY CHARACTERISTICS Power Supply Rejection Ratio Supply Current Power DissipationVINH VINL IIN tAQ 10 V Step 10 V Step k <30% Overshoot 10 V Step 10.8 V VDD 13.2 V
VDD +5.0 V, VSS 5.0 V, DGND = No Load, TA = Operating Temperature Range specified in Absolute Maximum Ratings, unless otherwise noted.)
Parameter Linearity Error Buffer Offset Voltage Hold Step Droop Rate Output Resistance Output Source Current 1 Output Sink Current1 Output Voltage Range LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Input Current DYNAMIC PERFORMANCE 2 Acquisition Time3 Acquisition Time3 Hold Mode Settling Time Slew Rate5 Capacitive Load Stability SUPPLY CHARACTERISTICS Power Supply Rejection Ratio Supply Current Power Dissipation Symbol VOS VHS V/t ROUT ISOURCE ISINK OVR VINH VINL IIN tAQ SR CL PSRR IDD PDIS +3 V Step +3 V Step k <30% Overshoot 5 V VDD 6 V Conditions VIN 0 V VIN to +85°C VIN = 40°C VIN = +25°C VIN 0 V VIN 20 k Min 10 Typ Max Units % mV mV/s µA µs V/µs mA mW
NOTES 1 Outputs are capable of sinking and sourcing over 20 mA, but linearity and offset are guaranteed at specified load levels. 2 All input control signals are specified with +5 V) and timed from a voltage level V. 3 This parameter is guaranteed without test. 4 Slew rate is measured in the sample mode with 10 V step from 80%. 5 Slew rate is measured in the sample mode with +3 V step from to 80%. Specifications are subject to change without notice.
VDD to DGND. 17 V VDD to VSS. 17 V VLOGIC to DGND. 0.3 V, VDD VIN to DGND. VSS, VDD VOUT to DGND. VSS, VDD Analog Output Current. 20 mA (Not Short-Circuit Protected) Digital Input Voltage to DGND. 0.3 V, VDD 0.3 V Operating Temperature Range EQ, EP, ES. to +85°C Junction Temperature. +150°C Storage Temperature. to +150°C Lead Temperature (Soldering, 60 sec). +300°C
*JA is specified for worst case mounting conditions, i.e., JA is specified for device in socket for cerdip and plastic DIP packages; JA is specified for device soldered to printed circuit board for SO package. CAUTION 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; function operation at or above this specification is not implied. Exposure to the above maximum rating conditions for extended periods may affect device reliability. 2. Digital inputs and outputs are protected; however, permanent damage may occur on unprotected units from high energy electrostatic fields. Keep units in conductive foam or packaging at all times until ready to use. Use proper antistatic handling procedures. 3. Remove power before inserting or removing units from their sockets.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SMP04 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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