Details, datasheet, quote on part number: SMP08FP
PartSMP08FP
CategoryAnalog & Mixed-Signal Processing => Amplifiers => Sample & Hold
DescriptionLow Droop Rate Octal Sample-and-hold With Multiplexed Input
CompanyAnalog Devices
DatasheetDownload SMP08FP datasheet
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Features, Applications

FEATURES Internal Hold Capacitors Low Droop Rate TTL/CMOS Compatible Logic Inputs Single or Dual Supply Operation Break-Before-Make Channel Addressing Compatible With CD4051 Pinout Low Cost APPLICATIONS Multiple Path Timing Deskew for ATE Memory Programmers Mass Flow/Process Control Systems Multichannel Data Acquisition Systems Robotics and Control Systems Medical and Analytical Instrumentation Event Analysis Stage Lighting Control

The is a monolithic octal sample-and-hold; it has eight internal buffer amplifiers, input multiplexer, and internal hold capacitors. It is manufactured in an advanced oxide isolated CMOS technology to obtain high accuracy, low droop rate, and fast acquisition time. The SMP08 has a typical linearity error of only 0.01% and can accurately acquire a 10-bit input signal 1/2 LSB in less than 7 microseconds. The SMP08's output swing includes the negative supply in both single and dual supply operation. The SMP08 was specifically designed for systems that use a calibration cycle to adjust a multiple of system parameters. The low cost and high level of integration make the SMP08 ideal for calibration requirements that have previously required an ASIC, or high cost multiple D/A converters.

The SMP08 is also ideally suited for a wide variety of sampleand-hold applications including amplifier offset or VCA gain adjustments. One or more SMP08s can be used with single or multiple DACs to provide multiple set points within a system. The SMP08 offers significant cost and size reduction over discrete designs. It is available a 16-pin plastic DIP, or surfacemount SOIC package.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 Analog Devices, Inc., 1996

Parameter Linearity Error Buffer Offset Voltage Hold Step Droop Rate Output Source Current Output Sink Current Output Voltage Range LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Input Current DYNAMIC PERFORMANCE Acquisition Time3 Hold Mode Settling Time Channel Select Time Channel Deselect Time Inhibit Recovery Time Slew Rate Capacitive Load Stability Analog Crosstalk

SUPPLY CHARACTERISTICS Power Supply Rejection Ratio Supply Current

Parameter Linearity Error Buffer Offset Voltage Hold Step Droop Rate Output Source Current Output Sink Current Output Voltage Range LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Low Voltage Logic Input Current DYNAMIC PERFORMANCE2 Acquisition Time3 Hold Mode Settling Time Channel Select Time Channel Deselect Time Inhibit Recovery Time Slew Rate Capacitive Load Stability Analog Crosstalk SUPPLY CHARACTERISTICS Power Supply Rejection Ratio Supply Current Symbol VOS VHS VCH/t ISOURCE ISINK

Conditions 60 mV VIN = +25C, VIN TA +85C, VIN 6 V VIN to +85C VIN = +25C, VIN 6 V VIN 6 V1 VIN 10 k Min Typ VIN mV of Final Value Max Units % mV mV/s s ns V/s dB mA

NOTES 1 Outputs are capable of sinking and sourcing over 20 mA but offset is guaranteed at specified load levels. 2 All input control signals are specified with +5 V) and timed from a voltage level V. 3 This parameter is guaranteed without test. 4 Slew rate is measured in the sample mode with 10 V step from to 80%. Specifications subject to change without notice.

VDD to DGND. 17 V VDD to VSS. 17 V VLOGIC to DGND. 0.3 V, VDD VIN to DGND. VSS, VDD VOUT to DGND. VSS, VDD Analog Output Current. 20 mA (Not Short-Circuit Protected) Operating Temperature Range FP, FS. to +85C Junction Temperature. +150C Storage Temperature. to +150C Lead Temperature (Soldering, 60 sec). +300C Package Type 16-Pin Plastic DIP (P) 16-Pin SOIC (S) JA* 33 27 Units C/W

13 CH0OUT TOP VIEW CH5OUT 5 (Not to Scale) 12 CH3OUT INH 6 VSS 7 DGND 11 A CONTROL 10 B CONTROL 9 C CONTROL

*JA is specified for worst case mounting conditions, i.e., JA is specified for device in socket for plastic DIP package; JA is specified for device soldered to printed circuit board for SO package.

CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SMP08 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.


 

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