|Category||Communication => Fiber Optics|
|Description||Semiconductor Solutions For High Speed Communications And Fiber Optic Applications|
|Company||Infineon Technologies Corporation|
|Datasheet||Download TITAN19244 datasheet
The Titan is a highly integrated single chip quadport STS-192 SONET/SDH TDM framer and pointer processor device. The Titan 19244 provides section, line, and path overhead processing for quad STS-192/STM-64. The framer itself takes four 10 Gbit/s (16-bit bus at 622 Mbit/s) channels on the line side interface, which is compliant with SFI-4 standard. The framer outputs four STS-192 SONET links on the system side. The system block diagram on the next page depicts a configuration for a quad OC-192 TDM framer and pointer processor application. The Titan 19244 is compliant with SONET/SDH standards ITU G.707, Bellcore GR-253, GR-1377, and ANSI T1.105.
Applications SONET/SDH Digital Cross-Connects SONET/SDH Terminal Multiplexers Long Haul and Metro Network ADM Dense Wave Division Multiplexers SONET/SDH Add/Drop Multiplexers Multi-Service Provisioning Platforms Features Quad-port STS-192/STM-64 SONET/SDH framer and pointer processor Terminates and generates section and line overhead layer for STS-192/STM-64 Supports pointer processing at STS-1 granularity for STS-192/STM-64 Supports flexible concatenation of payloads STS-48c,... STS-192c Performs frame synchronous scrambling and de-scrambling of STS-192
Drops/Inserts section and line overhead data bytes in the receive/transmit direction onto an external bus on both line side & system side Drops/Inserts Data Communications Channel (DCC) bytes on a serial link Provides hardware assistance for APS via & K2 bytes. A separate APS interrupt port is provided per port for quad STS-192/STM-64 Supports external timing mode Detects Severely Errored Framing (SEF), Loss Of Signal (LOS), Loss Of Frame (LOF), Loss Of Pointer (LOP), and Loss Of Clock (LOC) Monitors Line Alarm Indication Signal (AIS-L), Line Remote Defect Indication (RDI-L), and Line Remote Error Indication (REI-L) Handles section trace identifier (J0) and path trace identifier (J1) processing Calculates, monitors, and counts the Section BIP-8 (B1), Line BIP-8N (B2), and Path BIP-8 (B3) errors
Supports BER algorithm for Signal Fail (SF) and Signal Degrade (SD) Supports Terminal Loopback and Facility Loopback Supports Path REI error counting and Path RDI monitoring Supports detection of path unequipped and payload label mismatch (Signal Label Mismatch) Provides four 16-bit LVDS parallel buses operating at 622 Mbit/s on the line side for quad STS-192 Compliant with SFI-4 standard on the Line Side Interface Provides four 16-bit LVDS parallel buses at 622 MHz (STS-192 SONET links) on the system side Supports IEEE1149.1 JTAG testing Supports 32-bit MPC860 Motorola microprocessor interface Meets ITU GR-253, GR-1377, and ANSI T1.105 1413-pin flip-chip BGA package
RX_EDCC_DATA RX_EDCC_DVALID RX_LDCC_DATA [3:0] RX_LDCC_DVALID [3:0] RX_SDCC_DVALID [3:0] RX_SDCC_DATA [3:0] LN_DRP_CLK [3:0] 77.76 MHz LN_DRP_FRM_STR [3:0] LN_DRP_DVALID [3:0] LN_DRP_DATA [3:0][7:0] RX_LN_CLK [3:0] 622.08 MHz RX_LN_DATA [3:0][15:0] RX_LOF [3:0] RX_LIS [3:0] RX_LOC [3:0]Receive Pointer Processor & Path Processor Receive Pointer Aligner
SYS_ADD_ROW_STR [3:0] SYS_ADD_FRM_STR [3:0] SYS_ADD_CLK [3:0] 77.76 MHz SYS_INSRT_EN [3:0] SYS_ADD_DATA [3:0][7:0] RX_TDM_SYSCLK [3:0] 622.08 MHz RX_TDMDATA[3:0][15:0] RX_SYS_CLKI [3:0] 622.08 MHz SYS_FP [3:0]Receive Line Side Interface Block Transmit Line Side Interface Block
Transmit Framer System Side & Interface Descrambler Block
LN_ADD_CLK [3:0] 77.76 MHz LN_ADD_FMR_STR [3:0] LN_ADD_ROW_STR [3:0] LN_ADD_EN [3:0] LN_ADD_DATA [3:0][7:0] TX_SDCC_DATA [3:0] TX_SDCC_DVALID [3:0] TX_LDCC_DATA [3:0] TX_LDCC_DVALID [3:0] TX_EDCC_DATA TX_EDCC_DVALID
Advantages Low power Small footprint High integration STS-768 support SONET/SDH support Standards GR-253 GR-1377 ITU G.707 ANSI T1.105 Specifications 622 MHz LVDS I/Os 1413 ball FCBGA package Full-scan; JTAG; MemBIST 70 °C temperature range <12 W power requirement (typ.) Note: Specifications subject to change without notice.Infineon Technologies NA Corp. 1730 North First Street San Jose, CA 95112 USA
Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München © Infineon Technologies AG 2002. All Rights Reserved.
Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide.
Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in lifesupport devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Ordering No. B168-H8050-X-X-7600 Printed in Germany PS 05022. R&L
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