|Category||Memory => FIFO|
|Description||256 X 9 Syncfifo, 5.0V|
|Company||Integrated Device Technology, Inc.|
|Datasheet||Download 72251 datasheet
The IDT72421/72201/72211/72221/72231/72241/72251 SyncFIFOTM are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls. These devices have a and x 9-bit memory array, respectively. These FIFOs are applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and two write enable pins (WEN1, WEN2). Data is written into the Synchronous FIFO on every rising clock edge when the write enable pins are asserted. The output port is controlled by another clock pin (RCLK) and two read enable pins (REN1, REN2). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. An output enable pin (OE) is provided on the read port for three-state control of the output. The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF). Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are provided for improved system control. The programmable flags default to Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag offset loading is controlled by a simple state machine and is initiated by asserting the load pin (LD). These FIFOs are fabricated using IDT's high-speed submicron CMOS technology.
x 9-bit organization x 9-bit organization x 9-bit organization x 9-bit organization x 9-bit organization x 9-bit organization x 9-bit organization 10 ns read/write cycle time Read and Write Clocks can be independent Dual-Ported zero fall-through time architecture Empty and Full Flags signal FIFO status Programmable Almost-Empty and Almost-Full flags can be set to any depth Programmable Almost-Empty and Almost-Full flags default to Empty+7, and Full-7, respectively Output enable puts output data bus in high-impedance state Advanced submicron CMOS technology Available in the 32-pin plastic leaded chip carrier (PLCC) and 32-pin Thin Quad Flat Pack (TQFP) For through-hole product please see the IDT72420/72200/72210/ 72220/72230/72240 data sheet Industrial temperature range +85°C) is available
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a registered trademark of Integrated Device Technology, Inc.
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
Symbol Name D0-D8 Data Inputs RS Reset WCLK
Data Outputs Read Clock Read Enable 1 Read Enable 2 Output Enable Empty Flag Programmable Almost-Empty Flag Programmable Almost-Full Flag Full Flag Power Ground
I/O Description I Data inputs for a 9-bit bus. I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array,FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up. I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted. I If the FIFO is configured to have programmable flags, WEN1 is the only write enable pin. When WEN1 is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. I The FIFO is configured at reset to have either two write enables or programmable flags. WEN2/LD is HIGH at reset, this pin operates as a second write enable. WEN2/LD is LOW at reset, this pin operates as a control to load and read the programmable flag offsets. If the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag offsets. O Data outputs for a 9-bit bus. I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are asserted. I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. I When OE is LOW, the data output bus is active. OE is HIGH, the output data bus will in a high-impedance state. O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. O When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default offset at reset is Empty+7. PAE is synchronized to RCLK. O When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset at reset is Full-7. PAF is synchronized to WCLK. O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. One +5 volt power supply pin. One 0 volt ground pin.
Symbol VTERM TSTG IOUT Rating Terminal Voltage with Respect to GND Storage Temperature DC Output Current Com'l & Ind'l to +50 Unit °C mA
Symbol VCC GND VIH VIL TA Parameter Supply Voltage Commercial/Industrial Supply Voltage Input High Voltage Commercial/Industrial Input Low Voltage Commercial/Industrial Operating Temperature Commercial Operating Temperature Industrial Min. Typ. Max. Unit °C
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
(Commercial: VCC to +70°C; Industrial: VCC IDT72231 IDT72241 Com'l and Ind'l(1) tCLK ns Symbol Parameter Min. Typ. Max. ILI(2) ILO(3) VOH VOL ICC1
Input Leakage Current (Any Input) Output Leakage Current Output Logic "1" Voltage, IOH = 2mA Output Logic "0" Voltage, IOL = 8mA Active Power Supply Current Standby Current
NOTES: 1. Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product. 2. Measurements with 0.4 VIN VCC. 3. OE VIH, 0.4 VOUT VCC. 4. Tested with outputs open (IOUT 0). 5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz. 6. Typical + 0.02*CL*fS (in mA). These equations are valid under the following conditions: VCC fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching CL = capacitive load (in pF). 7. All Inputs = VCC 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
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