|Category||Memory => FIFO|
|Description||1K X 36 X 2 Syncbififo, 5.0V|
|Company||Integrated Device Technology, Inc.|
|Datasheet||Download 723644 datasheet
Memory storage capacity: x 2 Clock frequencies to 83 MHz (8 ns access time) Two independent clocked FIFOs buffering data in opposite directions Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags functions) or First Word Fall Through Timing (using ORA, ORB, IRA, and IRB flag functions) Programmable Almost-Empty and Almost-Full flags; each has three default offsets (8, 16 and 64)
Serial or parallel programming of partial flags Port B bus sizing of 36-bits (long word), 18-bits (word) and 9-bits (byte) Big- or Little-Endian format for word and byte bus sizes Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings Mailbox bypass registers for each FIFO Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Auto power down minimizes power dissipation Available in space saving 128-pin Thin Quad Flatpack (TQFP) Industrial temperature range +85°C) is availableRead Pointer Status Flag Logic EFB/ORB AEB
Status Flag Logic Read Pointer Write Pointer
IDT, the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
The is a monolithic, high-speed, lowpower, CMOS bidirectional synchronous (clocked) FIFO memory which supports clock frequencies to 83 MHz and has read access times as fast as 8 ns. Two independent x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. FIFO data on Port B can be input and output or 9-bit formats with a choice of Big- or Little-Endian configurations.
These devices are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.
Communication between each port may bypass the FIFOs via two mailbox registers. The mailbox register width matches the selected Port B bus width. Each Mailbox register has a flag (MBF1 and MBF2) to signal when new mail has been stored. Two kinds of reset are available on these FIFOs: Master Reset and Partial Reset. Master Reset initializes the read and write pointers to the first location of the memory array, configures the FIFO for Big- or Little-Endian byte arrangement and selects serial flag programming, parallel flag programming, or one of three possible default flag offset settings, or 64. There are two Master Reset pins, MRS1 and MRS2. Partial Reset also sets the read and write pointers to the first location of the memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e., programming method and partial flag default offsets) are retained. Partial Reset is useful since it permits flushing of the FIFO memory without changing any configuration settings. Each FIFO has its own, independent Partial Reset pin, PRS1 and PRS2. These devices have two modes of operation: In the IDT Standard mode, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In the First Word Fall Through mode (FWFT), the first long-word (36-bit wide) written to an empty FIFO appears automatically on the outputs, no read operation is required (nevertheless, accessing subsequent words does necessitate a formal read request). The state of the BE/FWFT pin during FIFO operation determines the mode in use. Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/IRB). The EF and FF functions are selected in the IDT Standard mode. EF indicates
whether or not the FIFO memory is empty. FF shows whether the memory is full or not. The IR and OR functions are selected in the First Word Fall Through mode. IR indicates whether or not the FIFO has available memory locations. OR shows whether the FIFO has data available for reading or not. It marks the presence of valid data on the outputs. Each FIFO has a programmable Almost-Empty flag (AEA and AEB) and a programmable Almost-Full flag (AFA and AFB). AEA and AEB indicate when a selected number of words remain in the FIFO memory. AFA and AFB indicate when the FIFO contains more than a selected number of words. FFA/IRA, FFB/IRB, AFA and AFB are two-stage synchronized to the port clock that writes data into its array. EFA/ORA, EFB/ORB, AEA and AEB are two-stage synchronized to the port clock that reads data from its array. Programmable offsets for AEA, AEB, AFA and AFB are loaded in parallel using Port or in serial via the SD input. The Serial Programming Mode pin (SPM) makes this selection. Three default offset settings are also provided. The AEA and AEB threshold can be set or 64 locations from the empty boundary and the AFA and AFB threshold can be set or 64 locations from the full boundary. All these choices are made using the FS0 and FS1 inputs during Master Reset. Two or more devices may be used in parallel to create wider data paths. If, at any time, the FIFO is not actively performing a function, the chip will automatically power down. During the power down state, supply current consumption (ICC) at a minimum. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state. The IDT723624/723634/723644 are characterized for operation from to 70°C. Industrial temperature range +85°C) is available. They are fabricated using IDT's high speed, submicron CMOS technology.
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