|Category||Memory => FIFO|
|Description||64 X 5 Asyncfifo, 5.0V|
|Company||Integrated Device Technology, Inc.|
|Datasheet||Download 72402 datasheet
First-ln/First-Out Dual-Port memory x 4 organization x 5 organization (IDT72402/72404) RAM-based FIFO with low falI-through time Low-power consumption Active: 175mW (typ.) Maximum shift rate 45MHz High data output drive capability Asynchronous and simultaneous read and write Fully expandable by bit width Fully expandable by word depth IDT72403/72404 have Output Enable pin to enable output data High-speed data communications applications High-performance CMOS technology Available in CERDIP, plastic DIP and SOIC Military product compliant to MlL-STD-883, Class B Standard Military Drawing #5962-86846 and 5962-89523 is listed on this function. Industrial temperature range +85°C) is available (plastic packages only)
The IDT72401 and IDT72403 are asynchronous highperformance First-ln/First-Out memories organized 64 words by 4 bits. The IDT72402 and IDT72404 are asynchronous high-performance First-ln/First-Out memories organized as
64 words by 5 bits. The IDT72403 and IDT72404 also have an Output Enable (OE) pin. The FlFOs accept or 5-bit data at the data input (D0-D3, 4). The stored data stack on a firstin/first-out basis. A Shift Out (SO) signal causes the data at the next to last word to be shifted to the output while all other data shifts down one location in the stack. The Input Ready (IR) signal acts like a flag to indicate when the input is ready for new data (IR = HIGH) or to signal when the FIFO is full (IR = LOW). The IR signal can also be used to cascade multiple devices together. The Output Ready (OR) signal is a flag to indicate that the output remains valid data (OR = HIGH) or to indicate that the FIFO is empty (OR = LOW). The OR can also be used to cascade multiple devices together. Width expansion is accomplished by logically ANDing the IR and OR signals to form composite signals. Depth expansion is accomplished by tying the data inputs of one device to the data outputs of the previous device. The IR pin of the receiving device is connected to the SO pin of the sending device and the OR pin of the sending device is connected to the Shift In (SI) pin of the receiving device. Reading and writing operations are completely asynchronous allowing the FIFO to be used as a buffer between two digital machines of widely varying operating frequencies. The 45MHz speed makes these FlFOs ideal for high-speed communication and controller applications. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B.READ MULTIPLEXER READ POINTER OUTPUT CONTROL LOGIC
The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor, Inc.
©1998 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
PLASTIC DIP (P16-1, order code: P) CERDIP (D16-1, order code: D) SOIC (SO16-1, order code: SO) TOP VIEW NOTES: 1. Pin - No Connection IDT72403 2. Pin - No Connection - IDT72404
PLASTIC DIP (P18-1, order code: P) CERDIP (D18-1, order code: D) SOIC (SO18-1, order code: SO) TOP VIEW
Symbol VTERM Rating Terminal Voltage with Respect to GND Storage Temp. DC Output Current Commercial to +7.0 Military to +7.0 Unit V
Symbol VCC GND Parameter Supply Voltage Commercial/Military Supply Voltage Input High Voltage Input High Voltage Operating Temperature Commercial Operating Temperature Military Min. Typ. Max. Unit °C
NOTE: 2747 tbl 01 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
IDT72403 IDT72404 Commercial fIN = 45,35,25,15,10 MHz Symbol IIL IIH VOL VOH ILZ(2) ICC(3,4) Parameter Low-Level Input Current High-Level Input Current Low-Level Output Voltage High-Level Output Voltage Output Short-Circuit Current HIGH Impedance Output Current LOW Impedance Output Current Active Supply Current Test Conditions VCC = Max., GND VI VCC = Max., GND VI VCC = Min., IOL = 8mA VCC = Min., IOH = -4mA VCC = Max., VO = GND VCC = Max., = 2.4V VCC = Max., = 0.4V VCC = Max., = 10MHz Min. Max. IDT72403 IDT72404 Military fIN = 35,25,15,10 MHz Min. Max. Unit µA mA
NOTES: 2747 tbl 1. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Guaranteed but not tested. 2. IDT72403 and IDT72404 only. 3. Tested with outputs open (IOUT OE is HIGH for IDT72403/72404. 4. For frequencies greater than 10MHz, ICC - 10MHz]) commercial, and ICC - 10MHz]) military.Symbol tSIH tSIL tIDS tIDH tSOH(1) tSOL tMRW tMRS tSIR tHIR tSOR
Parameter Shift in HIGH Time Shift in LOW TIme Input Data Set-up Input Data Hold Time Shift Out HIGH Time Shift Out LOW Time Master Reset Pulse Master Reset Pulse to SI Data Set-up to IR Data Hold from IR Data Set-up to OR HIGH
Parameter Shift In Rate Shift In to Input Ready LOW Shift In to Input Ready HIGH Shift Out Rate Shift Out to Output Ready LOW Shift Out to Output Ready HIGH Output Data Hold (Previous Word) Output Data Shift (Next Word) Data Throughput or "Fall-Through" Master Reset to OR LOW Master Reset to IR HIGH Master Reset to Data Output LOW Output Valid from OE LOW Output High-Z from OE HIGH Input Ready Pulse HIGH Output Ready Pulse HIGHfOUT tORL(1) tORH(1) tODH tODS tPT tMRORL tMRIRH tMRQ tOOE(3) tHZOE(3,4) tIPH
NOTES: 2747 tbl 06 1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. A monolithic ceramic capacitor of 0.1µF directly between VCC and GND with very short lead length is recommended. 2. This parameter applies to FIFOs communicating with each other in a cascaded mode. IDT FIFOs are guaranteed to cascade with other IDT FIFOs of like speed grades. 3. IDT72403 and IDT72404 only. 4. Guaranteed by design but not currently tested.
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