|Category||Memory => FIFO|
|Description||64 X 5 Asyncfifo W/output Enable+Flags, 5.0V|
|Company||Integrated Device Technology, Inc.|
|Datasheet||Download 72413 datasheet
First-ln/First-Out Dual-Port x 5 organization Low-power consumption Active: 200mW (typical) RAM-based internal structure allows for fast fall-through time Asynchronous and simultaneous read and write Expandable by bit width Cascadable by word depth Half-Full and Almost-Full/Empty status flags High-speed data communications applications Bidirectional and rate buffer applications High-performance CMOS technology Available in plastic DIP, CERDIP and SOIC Military product compliant to MIL-STD-883, Class B Industrial temperature range +85oC) is available (plastic packages only)
The x 5, high-speed First-In/First-Out (FIFO) that loads and empties data on a first-in-first-out basis. It is expandable in bit width. All speed versions are cascadable in depth. The FIFO has a Half-Full Flag, which signals when it has 32 or more words in memory. The Almost-Full/Empty Flag is active when there are 56 or more words in memory or when there are 8 or less words in memory. This device is pin and functionally compatible to the MMI67413. It operates at a shift rate of 45MHz. This makes it ideal for use in high-speed data buffering applications. This FIFO can be used as a rate buffer, between two digital systems of varying data rates, in high-speed tape drivers, hard disk controllers, data communications controllers and graphics controllers. The IDT72413 is fabricated using IDTs high-performance CMOS process. This process maintains the speed and high output drive capability of TTL circuits in low-power CMOS. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B.DATA 0-4 ) (MR) MASTER RESET INPUT READY SHIFT IN (IR)
(SO) INPUT CONTROL LOGIC REGISTER CONTROL LOGIC OUTPUT CONTROL LOGIC (OR)
The IDT logo is a registered trademark of Integrated Device Technology,Inc. FAST is a trademark of National Semiconductor, Inc.
©1998 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.Rating Terminal Voltage with Respect to GND Storage Temperature DC Output Current
NOTE: 2748 tbl 01 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PLASTIC DIP (P20-1, order code: P) CERDIP (D20-1, order code: D) SOIC (SO20-2, order code: SO) TOP VIEW
Parameter Supply Voltage Commercial/Military Supply Voltage Input High Voltage Input Low Voltage Operating Temperature Commercial Operating Temperature MilitarySymbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V
Symbol Parameter IIL Low-Level Input Current High-Level Input Current IIH Low-Level Output Current VOL
Test Conditions VCC = Max., GND VI VCC = Max., GND VI VCC = Min. IOL (Q0-4) Mil Com'l. IOL (IR, OR)(1) IOL (HF, AF/E) High-Level Output Current VCC = Min. IOH (Q0-4) IOH (IR, OR) IOH (HF, AF/E) Output Short-Circuit Current VCC = Max. = 0V HIGH Impedance Output Current VCC = Max. = 2.4V LOW Impedance Output Current VCC = Max. = 0.4V Active Supply Current VCC = Max., OE=HIGH Inputs LOW, f=25MHz
NOTES: 2748 tbl 04 1. Care should be taken to minimize as much as possible the DC and capactive load on IR and OR when operating at frequencies above 25mHz. 2. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. Guaranteed by design, but not currently tested. 3. Tested with outputs open (IOUT 0). 4. For frequencies greater than 25MHz, ICC - 25MHz]) commercial and ICC - 25MHz]) military.Symbol tSIH(1) tSIL(1) tIDS tIDH tSOH(1) tSOL tMRW tMRS
Parameter Shift in HIGH Time Shift in LOW TIme Input Data Set-up Input Data Hold Time Shift Out HIGH Time Shift Out LOW Time Master Reset Pulse Master Reset Pulse to SI
NOTE: 2748 tbl 05 1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. A monolithic ceramic capacitor of 0.1µF directly between VCC and GND with very short lead length is recommended.
Symbol fIN tIRL(1) tIRH(1) fOUT tORH(1) tODH(1) tODS tPT tMRORL tMRIRH(3) tMRIRL(2) tMRQ tMRHF tMRAFE tOPH(3) tORD(3) tAEH tAEL tAFL tAFH tHFH tHFL tPLZ(3) tPHZ(3)
Parameter Shift In Rate Shift In to Input Ready LOW Shift In to Input Ready HIGH Shift Out Rate Shift Out to Output Ready LOW Shift Out to Output Ready HIGH Output Data Hold Previous Word Output Data Shift Next Word Data Throughput or "Fall-Through" Master Reset to Output Ready LOW Master Reset to Input Ready HIGH Master Reset to Input Ready LOW Master Reset to Outputs LOW Master Reset to Half-Full Flag Master Reset to AF/E Flag Input Ready Pulse HIGH Output Ready Pulse HIGH Output Ready HIGH to Valid Data Shift Out to AF/E HIGH Shift In to AF/E Shift Out to AF/E LOW Shift In to AF/E HIGH Shift to HF HIGH Shift Out to HF LOW Output Disable Delay Output Enable Delay
NOTES: 2748 tbl 06 1. Since the FIFO is a very high-speed device, care must be taken in the design of the hardware and the timing utilized within the design. Device grounding and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. A monolithic ceramic capacitor of 0.1µF directly between VCC and GND with very short lead length is recommended. 2. If the FIFO is full, (IR = HIGH), MR forces to go LOW, and MR causes to go HIGH. 3. Guaranteed by design but not currently tested.
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