|Company||Integrated Device Technology, Inc.|
|Datasheet||Download 72521 datasheet
NOTE: The IDT72511/72521 have been obsoleted and the last time buy will on 01/29/2003. These devices should not be used in new designs. FEATURES:
The IDT72511 and IDT72521 are highly integrated first-in, first-out memories that enhance processor-to-processor and processor-to-peripheral communications. IDT BiFIFOs integrate two side-by-side memory arrays for data transfers in two directions. The BiFIFOs have two ports, A and B, that both have standard microprocessor interfaces. All BiFIFO operations are controlled from the 18-bit wide Port A. Port B is also 18 bits wide and can be connected to another processor or a peripheral controller. The BiFIFOs have a 9-bit bypass path that allows the device connected to Port A to pass messages directly to the Port B device. Ten registers are accessible through Port A, Command Register, a Status Register, and eight Configuration Registers. The IDT BiFIFO has programmable flags. Each FIFO memory array has four internal flags, Empty, Almost-Empty, Almost-Full and Full, for a total of eight internal flags. The Almost-Empty and Almost-Full flag offsets can be set to any depth through the Configuration Registers. These eight internal flags can be assigned to any of four external flag pins (FLGA-FLGD) through one Configuration Register. Port B has programmable I/O, reread/rewrite and DMA functions. Six programmable I/O pins are manipulated through two Configuration Registers. The Reread and Rewrite controls will read or write Port B data blocks multiple times. The BiFIFO has three pins, REQ, ACK and CLK, to control DMA transfers from Port B devices.
Two side-by-side FIFO memory arrays for bidirectional data transfers (IDT72521) 18-bit data buses on Port A side and Port B side Can be configured for or 36-to-36-bit communication Fast 35ns access time Fully programmable standard microprocessor interface Built-in bypass path for direct data transfer between two ports Two fixed flags, Empty and Full, for both the A-to-B and the Bto-A FIFO Two programmable flags, Almost-Empty and Almost-Full for each FIFO Programmable flag offset can be set to any depth in the FIFO Any of the eight flags can be assigned to four external flag pins Flexible reread/rewrite capabilities Six general-purpose programmable I/O pins Standard DMA control pins for data exchange with peripherals 68-pin PLCC package Industrial temperature range +85C) is availableData A Chip Select A Data Strobe A Read/Write A Addresses Data B Read B
I/O Data inputs and outputs for the 18-bit Port A bus. Port A is accessed when Chip Select A is LOW.Description
Data is written into Port A on the rising edge of Data Strobe when Chip Select is LOW. Data is read out of Port A on the falling edge of Data Strobe when Chip Select is LOW. This pin controls the read or write direction of Port A. When CSA is LOW and R/WA is HIGH, data is read from Port A on the falling edge of DSA. When CSA is LOW and R/WA is LOW, data is written into Port A on the rising edge of DSA. When Chip Select A is asserted, A0, A1, and Read/Write A are used to select one of six internal resources. Data inputs and outputs for the 18-bit Port B bus.
O If Port B is programmed to processor mode, this pin functions as an input. If Port B is programmed to peripheral mode this pin functions as an output. This pin can function as part of an Intel-style interface (RB) or as part of a Motorola-style interface (DSB). As an Intel-style interface, data is read from Port on a falling edge of RB. As a Motorola-style interface, data is read on the falling edge of DSB or written on the rising edge of DSB through Port B. The default is Intel-style processor mode. (RB as an input). O If Port B is programmed to processor mode, this pin functions as an input. If Port B is programmed to peripheral mode this pin functions as an output. This pin can function as part of an Intel-style interface (WB) or as part of a Motorola-style interface (R/WB). As an Intel-style interface, data is written to Port on a rising edge of WB. As a Motorola-style interface, data is read (R/WB = HIGH) or written (R/WB = LOW) to Port B in conjunction with a Data Strobe B falling or rising edge. The default is Intel-style processor mode (WB as an input.) Loads AB FIFO Read Pointer with the value of the Reread Pointer when LOW. Loads BA FIFO Write Pointer with the value of the Rewrite Pointer when LOW. Loads the Reread Pointer with the value of the AB FIFO Read Pointer when HIGH. Loads the Rewrite Pointer with the value of the BA FIFO Write Pointer when HIGH. When Port B is programmed in peripheral mode, asserting this pin begins a data transfer. Request can be programmed either active HIGH or active LOW. When Port B is programmed in peripheral mode, Acknowledge is asserted in response to a Request signal. This confirms that a data transfer may begin. Acknowledge can be programmed either active HIGH or active LOW. This pin is used to generate timing for ACK, RB, WB, DSB and R/WB when Port is in the peripheral mode. These four outputs pins can be assigned any one of the eight internal flags in the BiFIFO. Each of the two internal FIFOs (AB and BA) has four internal flags: Empty, Almost-Empty, Almost-Full and Full. Six general purpose I/O pins. The input or output direction of each pin can be set independently. A LOW on this pin will perform a reset of all BiFIFO functions. There are two +5V power pins. There are five Ground pins at 0V.Reread Rewrite Load Reread Load Rewrite Request Acknowledge Clock
PIO0-PIO5 Programmable I/O Inputs/ Outputs RS VCC GND Reset Power Ground I
|Some Part number from the same manufacture Integrated Device Technology, Inc.|
|72605 256 X 18 X 2 Bidirectional Syncfifo, 5.0V|
|7280 256x 9 Dualasync Fifo, 5.0V|
|72801 256 X 9 Dualsync Fifo, 5.0V|
|72805 256 X 18 Dualsync Fifo, 5.0V|
|7281 256x 9 Dualasync Fifo, 5.0V|
|72811 512 X 9 Dualsync Fifo, 5.0V|
|72815 256 X 18 Dualsync Fifo, 5.0V|
|7282 256x 9 Dualasync Fifo, 5.0V|
|72821 1K X 9 Dualsync Fifo, 5.0V|
|72825 256 X 18 Dualsync Fifo, 5.0V|
|7283 256x 9 Dualasync Fifo, 5.0V|
|72831 2K X 9 Dualsync Fifo, 5.0V|
|72835 256 X 18 Dualsync Fifo, 5.0V|
|7284 256x 9 Dualasync Fifo, 5.0V|
|72841 4K X 9 Dualsync Fifo, 5.0V|
|72845 256 X 18 Dualsync Fifo, 5.0V|
|7285 256x 9 Dualasync Fifo, 5.0V|
|72851 8K x9 Dualsync Fifo, 5.0V|
|728980 256 X 256 Time Slot Interchange Digital Switch, 5.0V|
|728981 128 X 128 Time Slot Interchange Digital Switch, 5.0V|
|728985 256 X 256 Time Slot Interchange Digital Switch, 5.0V|
IDT74FCT810CTDB : Fast CMOS Buffer/clock Driver
IDT72V291L20TFI : 3.3 VOLT HIGH Density CMOS Supersync FIFO 131,072 x 18 262,144 x 18
ICS853S314AFILFT : Clock/timing - Clock Buffers, Driver Integrated Circuit (ics) Fanout Buffer (Distribution), Multiplexer Tape & Reel (TR) 2.375 V ~ 3.465 V; IC FANOUT BUFFER 2-4 20-SSOP Specifications: Type: Fanout Buffer (Distribution), Multiplexer ; Frequency - Max: 2.7GHz ; Input: ECL, HSTL, LVPECL ; Output: ECL, LVPECL ; Voltage - Supply: 2.375 V ~ 3.465 V ; Package / Case: 20-SSOP (0.209", 5.30mm Width) ; Packaging: Tape & Reel (TR) ; Lead Free Status: Lead Free ; RoHS Sta
ICS843021AG-57LF : 640 MHz, OTHER CLOCK GENERATOR, PDSO24 Specifications: Device Type: Clock Generator ; Package Type: Surface Mount, TSSOP, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24 ; Supply Voltage: 2.97 to 3.63 volts ; Frequency: 40 MHz ; Operating Temperature: 0.0 to 70 C (32 to 158 F)
IDT70824L35PFBG : 4K X 16 STANDARD SRAM, 20 ns, CPGA84 Specifications: Memory Category: SRAM Chip ; Density: 66 kbits ; Number of Words: 4 k ; Bits per Word: 16 bits ; Package Type: PGA-84 ; Pins: 84 ; Logic Family: CMOS ; Supply Voltage: 5V ; Access Time: 20 ns ; Operating Temperature: 0 to 70 C (32 to 158 F)
IDT70V26S35JG : 16K X 16 DUAL-PORT SRAM, 25 ns, PQFP100 Specifications: Memory Category: SRAM Chip ; Density: 262 kbits ; Number of Words: 16 k ; Bits per Word: 16 bits ; Package Type: TQFP, PLASTIC, TQFP-100 ; Pins: 100 ; Logic Family: CMOS ; Supply Voltage: 3.3V ; Access Time: 25 ns ; Operating Temperature: 0 to 70 C (32 to 158 F)
IDT71V3556XSA166BG : 256K X 18 ZBT SRAM, 5 ns, PBGA119 Specifications: Memory Category: SRAM Chip ; Density: 4719 kbits ; Number of Words: 256 k ; Bits per Word: 18 bits ; Package Type: BGA, 14 X 22 MM, PLASTIC, BGA-119 ; Pins: 119 ; Logic Family: CMOS ; Supply Voltage: 3.3V ; Access Time: 5 ns ; Operating Temperature: 0 to 70 C (32 to 158 F)
IDT723643L15PFG : 1K X 36 OTHER FIFO, 11 ns, PQFP120 Specifications: Memory Category: FIFO ; Density: 37 kbits ; Number of Words: 1 k ; Bits per Word: 36 bits ; Package Type: TQFP, TQFP-120 ; Pins: 120 ; Logic Family: CMOS ; Supply Voltage: 5V ; Access Time: 11 ns ; Cycle Time: 15 ns ; Operating Temperature: 0 to 70 C (32 to 158 F)
5991A-2JI : 5991 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 Specifications: Device Type: Clock Driver ; Package Type: Surface Mount, PLASTIC, LCC-32 ; Supply Voltage: 4.75 to 5.25 volts ; Skew: 1000 ps ; Frequency: 100 MHz ; Operating Temperature: 0.0 to 70 C (32 to 158 F)
BUK474-200A : BUK474-200A/B; Powermos Transistor ISOlated Version of BUK454-200A/B. N-channel enhancement mode field-effect power transistor in a plastic full-pack envelope. The device is intended for use in Switched Mode Power Supplies (SMPS), motor control, welding, DC/DC and AC/DC converters, and in general purpose switching applications. SYMBOL VDS ID Ptot RDS(ON) PARAMETER BUK474 Drain-source voltage Drain current (DC) Total power.
CXG1120EN : Low Noise Amplifier With Bypass Switch/mixer. The is a low noise amplifier with a bypass switch/mixer MMIC for Japan CDMA (JCDMA) cellular. This IC is designed using the Sony's GaAs J-FET process. High gain Low noise amplifier (LNA) high current mode: = 15.0dB (Typ.) Mixer: = 12.0dB (Typ.) Low noise Low noise amplifier (LNA) high current mode: = 1.3dB (Typ.) Mixer: = 3.8dB (Typ.) Low distortion.
DFB54 : 2135a 3500v Disc Fast Recovery Diode. APPLICATIONS s Power Supplies s Freewheel Diode s Battery Chargers s D.C. Motor Control s Welding s Rectification s Double Side Cooling s High Surge Capability s Low Recovery Charge Type Number Repetitive Peak Reverse Voltage VRRM V Conditions Outline type code: DO200AD. See Package Details for further information. Symbol Double Side Cooled IF(AV) IF(RMS).
MA3J745D : VRM(V) = 30 ;; IF(mA) = 30 ;; VFmax.(V) = 0.3 ;; IR(µA) = 30 ;; Package = SMini3-G1.
MC33025 : Others. High Speed Double-ended PWM Controller. The MC34025 series are high speed, fixed frequency, doubleended pulse width modulator controllers optimized for high frequency operation. They are specifically designed for OffLine and DCtoDC converter applications offering the designer a cost effective solution with minimal external components. These integrated circuits feature an oscillator, a temperature.
XZMD55W-3 : Material (Color) = InGaAlP(Red);; Lens = Water Clear;; Peak Wave Length = 640;; Iv(ucd) If@10mA Min.= 280;; Iv(ucd) If@10mA Typ.= 595.
2520AN103J1 : HIGH Voltage Capacitors Monolithic Ceramic TYPE.
ML62A : Positive Voltage Regulator. Battery Powered Equipment Palmtops Portable Cameras and Video Recorders Reference Voltage Sources CMOS Low Power Consumption : Typical V out=5.0V Output V oltage Range in 0.1V increments Highly Accurate : Output V oltage + 2% Maximum Output Current: 250mA (within the maximum power dissipation V out=5.0V) Small Input-Output V oltage Differential at 100mA.
V22ZA3P : Varistor Products - Low to Medum Voltage, Radial Lead. The ZA Series of transient voltage surge suppressors are radial-lead varistors (MOVs) designed for use in the protection of low and mediumvoltage circuits and systems. Typical applications include motor control, telecom, automotive systems, solenoid, and power supply circuits to protect circuit board components and maintain data integrity. These devices.
PJU12106TF : Plastic, Fiberglass/Polyester PCB Supports, Twist Latch Box Boxes, Enclosures, Rack Box with Mounting Flange; BOX FIBER 12.5X10.7X7.01" GREY. s: Color: Gray ; Design: Hinged Door, Lid ; : PCB Supports, Twist Latch ; Material: Plastic, Fiberglass/Polyester ; Ratings: IP66, NEMA 1,2,3,4,4X,12,13, UL-508 ; Shipping Info: Shipped from Digi-Key ; Size / Dimension:.
8A4006-325 : PLUG, M12, 4WAY, PG9. s: Accessory Type: Sensor Lead ; For Use With: -.
OSTH404505D : Free Hanging (In-Line) Terminal Block - Headers, Plug And Socket Connectors, Interconnect Plug, Female Sockets; CONN PLUG HEADER 4PS 5.08MM. s: Terminal Block Type: Plug, Female Sockets ; Positions Per Level: 4 ; Pitch: 0.200" (5.08mm) ; Number of Levels: 1 ; Header Orientation: - ; Plug Wire Entry: 270° ; Termination: Screwless - Push In ; Wire Gauge:.
MCA12060D1331BP100 : 1.33K Ohm 0.25W, 1/4W Chip Resistor - Surface Mount; RES 1.33K OHM 1/4W .1% SMD 1206. s: Resistance (Ohms): 1.33K ; Power (Watts): 0.25W, 1/4W ; Tolerance: ±0.1% ; Packaging: Tape & Reel (TR) ; Composition: Thin Film ; Temperature Coefficient: ±25ppm/°C ; Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant.
BZY91C9V1N : Tv - Diode Circuit Protection 6.2V 5000W; DIODE TVS 9.1V 5000W STUD CATHOD. s: Package / Case: DO-203AB, DO-5, Stud ; Packaging: Bulk ; Polarization: Unidirectional ; Power (Watts): 5000W ; Voltage - Reverse Standoff (Typ): 6.2V ; Voltage - Breakdown: 8.5V ; Lead Free Status: Contains Lead ; RoHS Status: RoHS Non-Compliant.
L1795A : 15 A, BARRIER STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK. s: Mounting Options: Universal Mounting Foot, Panel Mount ; nb of Contacts: 12 ; Body Material: BRASS ; Current Rating: 15 amps ; Termination Options: Screw Clamp.
SAEEB837MBA0F00 : 1 FUNCTIONS, 837.5 MHz, SAW FILTER. s: Filter Design: Saw Filter ; Package Type: Surface Mount ; Operating Temperature: -22 to 185 F (243 to 358 K).