|Category||Memory => FIFO|
|Description||256x 9 Dualasync Fifo, 5.0V|
|Company||Integrated Device Technology, Inc.|
|Datasheet||Download 7280 datasheet
|CMOS DUAL ASYNCHRONOUS FIFO DUAL x 9, DUAL x 9, DUAL x 9, DUAL x 9, DUAL x 9, DUAL x 9
The IDT7280/7281/7282/7283/7284/7285 are dual-FIFO memories that load and empty data on a first-in/first-out basis. These devices are functional and compatible to two IDT7200/7201/7202/7203/7204/7205 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. The devices use Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. The reads and writes are internally sequential through the use of ring pointers, with no address information required to load and unload data. Data is toggled in and out of the devices through the use of the Write (W) and Read (R) pins. The devices utilize a 9-bit wide data array to allow for control and parity bits at the user's option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking. It also features a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW to allow for retransmission from the beginning of data. A Half-Full Flag is available in the single device mode and width expansion modes. These FIFOs are fabricated using IDT's high-speed CMOS technology. They are designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.
The IDT7280 is equivalent to two x 9 FIFOs The IDT7281 is equivalent to two x 9 FIFOs The IDT7282 is equivalent to two x 9 FIFOs The IDT7283 is equivalent to two x 9 FIFOs The IDT7284 is equivalent to two x 9 FIFOs The IDT7285 is equivalent to two x 9 FIFOs Low power consumption Active: 685 mW (max.) Power-down: 83 mW (max.) Ultra high speed--12 ns access time Asynchronous and simultaneous read and write Offers optimal combination of data capacity, small foot print and functional flexibility Ideal for bi-directional, width expansion, depth expansion, bus-matching, and data sorting applications Status Flags: Empty, Half-Full, Full Auto-retransmit capability High-performance CMOS technology Space-saving TSSOP Industrial temperature range +85°C) is availableDATA INPUTS (DA0-DA8) WA WRITE CONTROL WRITE POINTER THREESTATE BUFFERS RAM ARRAY x 9
READ CONTROL FLAG LOGIC EXPANSION LOGIC
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
Symbol VTERM TSTG IOUT Rating Terminal Voltage with Respect to GND Storage Temperature DC Output Current Com'l & Ind'l to +50 Unit °C mA
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Symbol VCC GND VIL(2) TA Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Operating Temperature Commercial Operating Temperature Industrial Min. Typ. 5.0 0 Max. Unit °C
NOTES: 1. For RT/RS/XI input, VIH = 2.6V (commercial). 2. 1.5V undershoots are allowed for 10ns once per cycle.
Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic "1" Voltage IOH = 2mA Output Logic "0" Voltage IOL = 8mA Active Power Supply Current (both FIFOs) Standby Current (R=W=RS=FL/RT=VIH)
NOTES: 1. Industrial temperature range product for the 15ns speed grade is available as a standard device. 2. Measurements with 0.4 VIN VCC. 3. R VIH, 0.4 VOUT VCC. 4. Tested with outputs open (IOUT 0). 5. Tested = 20 MHz. 6. Typical + 0.02*CL*fS] (in mA) with VCC fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching CL = capacitive load (in pF). 7. All Inputs = VCC 0.2V or GND + 0.2V.
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Condition VIN = 0V VOUT = 0V Max. 8 Unit pF
Symbol tS tRC tA tRR tRPW tRLZ tWLZ tDV tRHZ tWC tWPW tWR tDS tDH tRSC tRS tRSS tRSR tRTC tRT tRTS tRTR tEFL tHFH,FFH tRTF tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF tXOL tXOH tXI tXIR tXIS Shift Frequency Read Cycle Time Access Time
Read Recovery Time Read Pulse Width(3) Read Pulse Low to Data Bus at Low Z(4) Write Pulse High to Data Bus at Low Z Data Valid from Read Pulse High Read Pulse High to Data Bus at High Z Write Cycle Time Write Pulse Width(3) Write Recovery Time Data Set-up Time Data Hold Time Reset Cycle Time Reset Pulse Width(3) Reset Set-up Time(4) Reset Recovery Time Retransmit Cycle Time Retransmit Pulse Width(3) Retransmit Set-up Time(4) Retransmit Recovery Time Reset to Empty Flag Low Reset to Half-Full and Full Flag High Retransmit Low to Flags Valid Read Low to Empty Flag Low Read High to Full Flag High Read Pulse Width after EF High Write High to Empty Flag High Write Low to Full Flag Low Write Low to Half-Full Flag Low Read High to Half-Full Flag High Write Pulse Width after FF High Read/Write to XO Low Read/Write to XO High XI Pulse Width(3) XI Recovery Time XI Set-up Time
NOTES: 1. Timings referenced in AC Test Conditions. 2. Industrial temperature range product for the 15ns speed grade is available as a standard device. 3. Pulse widths less than minimum value are not allowed. 4. Values guaranteed by design, not currently tested. 5. Only applies to read data flow-through mode.
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