|Category||Communication => Network => Ethernet/DS1/E1 (T1/E1) => Switches|
|Description||256 X 256 Time Slot Interchange Digital Switch, 5.0V|
|Company||Integrated Device Technology, Inc.|
|Datasheet||Download 728980 datasheet
x 256 channel non-blocking switch Serial Telecom Bus Compatible (ST-BUS®) RX inputs--32 channels at 64 Kbit/s per serial line TX output--32 channels at 64 Kbit/s per serial line Three-state serial outputs Microprocessor Interface (8-bit data bus) 5V Power Supply Available in 44-pin Plastic Leaded Chip Carrier (PLCC), 40-pin Plastic Dip (P-DIP) and 44-pin Plastic Quad Flatpack (PQFP) Operating Temperature Range to +85°C
outputs, each of which consists of 32 channels (64 Kbit/s per channel) to form a multiplexed 2.048 Mb/s stream.
A functional block diagram of the IDT728980 device is shown on below. The serial ST-BUS® streams operate continuously at 2.048 Mb/s and are arranged in 125µs wide frames each containing 32, 8-bit channels. Eight input (RX0-7) and eight output (TX0-7) serial streams are provided in the IDT728980 device allowing a complete x 256 channel non-blocking switch matrix to be constructed. The serial interface clock (C4i) for the device is 4.096 MHz. The received serial data is internally converted to a parallel format by the on chip serial-to-parallel converters and stored sequentially a 256-position Data Memory. By using an internal counter that is reset by the input 8 KHz frame pulse, F0i, the incoming serial data streams can be framed and sequentially addressed. Data to be output on the serial streams may come from two sources: Data Memory or Connection Memory. The Connection Memory is 16 bits wide and
The is a ST-BUS® compatible digital switch controlled by a microprocessor. The IDT728980 can handle as many 256, 64 Kbit/s input and output channels. Those 256 channels are divided into 8 serial inputs andData Memory Control Register Connection Memory
PLASTIC DIP: 0.10in. pitch, 0.60in. (P40-1, order code: P) TOP VIEW
Ground. VCC Data Acknowledgment (Open Drain) RX Input to 7 Frame Pulse Clock Address to 5 Data Strobe Read/Write Chip Select Data Bus 7 TX Outputs to 7 (Three-state Outputs) Output Drive Enable Control Channel OutputDESCRIPTION
Ground Rail. +5.0 Volt Power Supply. This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this output. Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s. This input identifies frame synchronization signals formatted to ST-BUS® specifications. 4.096 MHz serial clock for shifting data in and out of the data streams. These lines provide the address to IDT728980 internal registers. This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with CS to enable the internal read and write generation. This input controls the direction of the data bus lines (D0-D7) during a microprocessor access. Active LOW input enabling a microprocessor read or write of control register or internal memories. These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH, Connection Memory LOW and data memory. Serial data output streams. These streams are composed 32, 64 Kbit/s channels at data rates of 2.048 Mb/s. This is an output enable for the TX0-7 serial outputs. If this input is LOW, TX0-7 are high-impedance. If this is HIGH, each channel may still be put into high-impedance by software control. This output a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the contents of the CCO bit in the Connection Memory HIGH locations.
is split into two 8-bit blocks--Connection Memory HIGH and Connection Memory LOW. Each location in Connection Memory is associated with a particular channel in the output stream as to provide a one-to-one correspondence between the two memories. This correspondence allows for per channel control for each TX output stream. In Processor Mode, data output on the TX stream is taken from the Connect Memory Low and originates from the microprocessor (Figure 2). Where as in Connection Mode (Figure 1), data is read from Data Memory using the address in Connection Memory. Data destined for a particular channel on the serial output stream is read during the previous channel time slot to allow time for memory access and internal parallelto-serial conversion. CONNECTION MODE In Connection Mode, the addresses of input source for all output channels are stored in the Connect Memory Low. The Connect Memory Low locations are mapped to corresponding x 32-channel output. The contents of the Data Memory at the selected address are then transferred to the parallel-toserial converters. By having the output channel to specify the input channel through the connect memory, input channels can be broadcast to several output channels. PROCESSOR MODE In Processor Mode the CPU writes data to specific Connect Memory Low locations which are to be output on the TX streams. The contents of the Connect Memory Low are transferred to the parallel-to-serial converter one channel before to be output and are transmitted each frame to the output until it is changed by the CPU. CONTROL The Connect Memory High bits (Table 4) control the per-channel functions available in the IDT728980. Output channels are selected into specific modes such as: Processor Mode or Connection mode and Output Drivers Enabled or in three-state condition. There is also one bit to control the state of the CCO output pin. OUTPUT DRIVE ENABLE (ODE) The ODE pin is the master output control pin. If the ODE input is held LOW all TDM outputs will be placed in high impedance regardless Connect Memory High programming. However, if ODE is HIGH, the contents of Connect Memory High control the output state on a per-channel basis. DELAY THROUGH THE IDT728980 The transfer of information from the input serial streams to the output serial streams results in a delay through the device. The delay through the IDT728980 device varies according to the combination of input and output streams and the
movement within the stream from channel to channel. Data received on an input stream must first be stored in Data Memory before it is sent out. As information enters the IDT728980 it must first pass through an internal serial-to-parallel converter. Likewise, before data leaves the device, it must pass through the internal parallel-to-serial converter. This data preparation has an effect on the channel positioning in the frame immediately following the incoming frame-mainly, data cannot leave in the same time slot, or in the time slot immediately following. Therefore, information that to be output in the same channel position as the information is input, relative to the frame pulse, will be output in the following frame. As well, information switched to the channel immediately following the input channel will not be output in the time slot immediately following, but in the next timeslot allocated to the output channel, one frame later. Whether information can be output during a following timeslot after the information entered the IDT728980 depends on which RX stream the channel information enters on and which TX stream the information leaves on. This is caused by the order in which input stream information is placed into Data Memory and the order in which stream information is queued for output. Table 1 shows the allowable input/output stream combinations for the minimum 2 channel delay.
If the A5 address line input is LOW then the IDT728980 Internal Control Register is addressed. If A5 input line is high, then the remaining address input lines are used to select the 32 possible channels per input or output stream. The address input lines and the Stream Address bits (STA) of the Control register give the user the capability of selecting all positions of IDT728980 Data and Connection memories. The IDT728980 memory mapping is illustrated in Table 2 and Figure 3. The data in the control register (Table 3) consists of Memory Select and Stream Address bits, Split Memory and Processor Mode bits. In Split Memory mode (Bit 7 of the Control register) reads are from the Data Memory and writes are to the Connect Memory as specified by the Memory Select Bits (Bits 4 and 3 of the Control Register). The Memory Select bits allow the Connect Memory High or LOW or the Data Memory to be chosen, and the Stream Address bits define internal memory subsections corresponding to input or output streams. The Processor Enable bit (bit 6) places EVERY output channel on every output stream in Processor Mode; i.e., the contents of the Connect Memory LOW (CML, see Table 5) are output on the TX output streams once every frame unless the ODE input pin is LOW. If PE bit is HIGH, then the IDT728980 behaves as if bits 2 (Channel Source) and 0 (Output Enable) of every Connect Memory High (CMH) locations were set to HIGH, regardless of the actual value. PE is LOW, then bit 2 and 0 of each Connect Memory High location operates normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output channel is in Processor Mode. If bit 2 of the CMH is LOW, then the contents of the CML define the source information (stream and channel) of the time slot that to be switched to an output.
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