Details, datasheet, quote on part number: IDT7006S55JB
PartIDT7006S55JB
CategoryMemory => Memory Chips => 6477019
Title16K X 8 DUAL-PORT SRAM, 15 ns, PQFP68
Description
CompanyIntegrated Device Technology, Inc.
DatasheetDownload IDT7006S55JB datasheet
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Specifications 
Memory CategorySRAM Chip
Density131 kbits
Number of Words16 k
Bits per Word8 bits
Package Type0.970 X 0.970 INCH, 0.080 INCH HEIGHT, GREEN, FP-68
Pins68
Logic FamilyCMOS
Supply Voltage5V
Access Time15 ns
Operating Temperature0 to 70 C (32 to 158 F)

 

Features, Applications
Features

True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access Military: 20/25/35/55/70ns (max.) Industrial: 55ns (max.) Commercial: 15/17/20/25/35/55ns (max.) Low-power operation IDT7006S Active: 750mW (typ.) Standby: 5mW (typ.) IDT7006L Active: 700mW (typ.) Standby: 1mW (typ.) IDT7006 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device

M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Devices are capable of withstanding greater than 2001V electrostatic discharge Battery backup operation--2V data retention TTL-compatible, single 5V (10%) power supply Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin TQFP Industrial temperature range +85C) is available for selected speed Green parts available, see ordering information

NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull.

Description

The is a high-speed x 8 Dual-Port Static RAM. The IDT7006 is designed to be used as a stand-alone 128K-bit Dual-Port RAM as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach 16-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 750mW of power. Low-power (L) versions offer battery backup data retention capability with typical power consumption of 500W from a 2V battery. The IDT7006 is packaged in a ceramic 68-pin PGA, an 68-pin quad flatpack, a PLCC, and a 64-pin thin quad flatpack, TQFP. Military grade product is manufactured in compliance with the latest revision of MIL-PRF38535 QML, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.

NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. J68-1 package body in x.95 in. x.17 in. F68-1 package body in x.08 in. PN64-1 package body is approximately 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking


NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately in x.16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking

Left Port CEL R/WL OEL - I/O7L SEML INTL BUSYL CER R/WR OER - I/O7R SEMR INTR BUSYR M/S VCC GND Right Port Chip Enable Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Interrupt Flag Busy Flag Master or Slave Select Power Ground


 

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