Details, datasheet, quote on part number: IDT7008L55
PartIDT7008L55
CategoryMemory => Memory Chips => 6477350
Title64K X 8 DUAL-PORT SRAM, 15 ns, CPGA84
Description
CompanyIntegrated Device Technology, Inc.
DatasheetDownload IDT7008L55 datasheet
Specifications 
Memory CategorySRAM Chip
Density524 kbits
Number of Words64 k
Bits per Word8 bits
Package Type1.12 X 1.12 INCH, 0.16 INCH HEIGHT, PGA-84
Pins84
Logic FamilyCMOS
Supply Voltage5V
Access Time15 ns
Operating Temperature0 to 70 C (32 to 158 F)

 

Features, Applications
Features

True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access Commercial: 15/20/25/35/55ns (max.) Industrial: 20/55ns (max.) Military: 25/35/55ns (max.) Low-power operation IDT7008S Active: 750mW (typ.) Standby: 5mW (typ.) IDT7008L Active: 750mW (typ.) Standby: 1mW (typ.) Dual chip enables allow for depth expansion without external logic

IDT7008 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port TTL-compatible, single 5V (10%) power supply Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP Industrial temperature range +85C) is available for selected speeds

NOTES: 1. BUSY is an input as a Slave (M/S = VIL) and an output when is a Master (M/S = VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

The is a high-speed x 8 Dual-Port Static RAM. The IDT7008 is designed to be used as a stand-alone 512K-bit Dual-Port RAM as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach 16-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for

Description

reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (CE0 and CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 750mW of power. The IDT7008 is packaged a 84-pin Ceramic Pin Grid Array (PGA), a 84-pin Plastic Leadless Chip Carrier (PLCC) and a 100-pin Thin Quad Flatpack (TQFP).


NOTES: 1. This text does not indicate orientation of the actual part marking. 2. All Vcc pins must be connected to power supply. 3. Package body is approximately in x.17 in. 4. This package code is used to reference the package diagram. 5. All GND pins must be connected to ground supply.

NOTES: 1. This text does not indicate orientation of the actual part marking. 2. All Vcc pins must be connected to power supply. 3. Package body is approximately 1.4mm. 4. This package code is used to reference the package diagram. 5. All GND pins must be connected to ground supply.


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