Details, datasheet, quote on part number: IDT70121L
PartIDT70121L
Category
DescriptionHigh-speed 2k X 9 Dual-port Static RAM With Busy & Interrupt
CompanyIntegrated Device Technology, Inc.
DatasheetDownload IDT70121L datasheet
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Features, Applications
HIGH-SPEED x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT

High-speed access Commercial: 25/35/45/55ns (max.) Low-power operation IDT70121/70125S Active: 500mW (typ.) Standby: 5mW (typ.) IDT70121/70125L Active: 500mW (typ.) Standby: 1mW (typ.) Fully asychronous operation from either port MASTER IDT70121 easily expands data bus width to 18 bits or more using SLAVE IDT70125 chip On-chip port arbitration logic (IDT70121 only) BUSY output flag on Master; BUSY input on Slave INT flag for port-to-port communication Battery backup operation--2V data retention TTL-compatible, signal 5V 10%) power supply Available in 52-pin PLCC Industrial temperature range +85C) is available, tested to military electrical specifications

The IDT70121/IDT70125 are high-speed x 9 Dual-Port Static RAMs. The IDT70121 is designed to be used as a stand-alone 9-bit Dual-Port RAM as a "MASTER" Dual-Port RAM together with the IDT70125 "SLAVE" Dual-Port in 18bit-or-more word width systems. Using the IDT MASTER/ SLAVE Dual-Port RAM approach in 18-bit-or-wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power-down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT70121/IDT70125 utilizes a 9-bit wide data path to allow for Data/Control and parity bits at the user's option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking.

NOTES: 1. 70121 (MASTER): BUSY is non-tristated push-pull output. 70125 (SLAVE): BUSY is input. 2. INT is totem-pole output.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

IDT 70121/70125S/L HIGH-SPEED x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT

Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 500mW of power. Low-power (L) versions offer battery backup data

retention capability with each port typically consuming 200W from a 2V battery. The IDT70121/IDT70125 devices are packaged a 52-pin PLCC.


Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min.

NOTES: 1. All Vcc pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. This text does not indicate the orientation of the actual part-marking.

NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 0.5V.

Unit C mA Symbol CIN COUT Parameter Input Capacitance Output Capacitance Condition(2) VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF

Rating Terminal Voltage with Respect to GND Operating Temperature Under Bias Storage Temperature DC Output Current

NOTES: 2654 tbl 13 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 3V or from to 0V.

NOTES: 2654 tbl 01 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty. 2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time or 10ns maximum, and is limited < 20mA for the period of VTERM > Vcc + 0.5V.

IDT 70121/70125S/L HIGH-SPEED x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC 10%)
Parameter Input Leakage Current(5) Output Leakage Current Output Low Voltage Output High Voltage

DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1,4) (VCC 10%)

Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports--TTL Level Inputs) Standby Current (One Port--TTL Level Inputs) Full Standby Current (Both Ports CMOS Level Inputs) Full Standby Current (One Port CMOS Level Inputs) Test Condition

NOTES: 1. "X" in part numbers indicates power rating (S or L). f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using "AC TEST CONDITIONS" of input levels of GND = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. Vcc=5V, TA=+25C for Typical values, and they are not production tested. 5. Port "A" may be either left or right port. Port "B" is opposite from port "A".


 

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