Details, datasheet, quote on part number: ISL5961
CategoryAnalog & Mixed-Signal Processing
Description14-Bit, +3.3V, 210MSPS, Commlink High Speed D/A Converter (TSSOP)
CompanyIntersil Corporation
DatasheetDownload ISL5961 datasheet
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Features, Applications

The 14-bit, 130/210+MSPS (Mega Samples Per Second), CMOS, high speed, low power, D/A (digital to analog) converter, designed specifically for use in high performance communication systems such as base transceiver stations utilizing or 3G cellular protocols. This device complements the CommLink ISL5x61 family of high speed converters, which include 10, 12, and 14-bit devices.


Speed Grades. 130M and 210+MSPS Low Power. 103mW with 20mA Output at 130MSPS Adjustable Full Scale Output Current. 20mA +3.3V Power Supply 3V LVCMOS Compatible Inputs Excellent Spurious Free Dynamic Range (75dBc to Nyquist, = 130MSPS, fOUT = 10MHz) UMTS Adjacent Channel Power at 19.2MHz EDGE/GSM SFDR in 20MHz Window Pin compatible, 3.3V, Lower Power Replacement For The AD9754 and HI5960



Cellular Infrastructure - Single or Multi-Carrier: IS-136, IS95, GSM, EDGE, CDMA2000, WCDMA, TDS-CDMA BWA Infrastructure Medical/Test Instrumentation Wireless Communication Systems High Resolution Imaging Systems Arbitrary Waveform Generators


CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2001, All Rights Reserved CommLinkTM is a trademark of Intersil Americas Inc.

(13) D0 (LSB) (14) CLK (28) 50 BEAD 10H 0.1F DCOM (26) DVDD (27) (20) ACOM (24) AVDD (23) COMP 0.1 F FERRITE BEAD + +3.3V (VDD) Z1:Z2 (22) IOUTA (21) IOUTB 50 (18) FSADJ RSET (50) REPRESENTS ANY 50 LOAD NC (15) SLEEP (16) REFLO (17) REFIO 0.1 F ONE CONNECTION DCOM ACOM


PIN NO. PIN NAME D13 (MSB) Through D0 (LSB) SLEEP REFLO REFIO FSADJ NC IOUTB IOUTA COMP AV DD ACOM DCOM DV DD CLK DESCRIPTION Digital Data Bit 13, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit). Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin has internal 20A active pulldown current. Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference. Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is enabled. Use 0.1F cap to ground when internal reference is enabled. Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current 32 x VFSADJ/RSET. No Connect. These should be grounded, but can be left disconnected. The complementary current output of the device. Full scale output current is achieved when all input bits are set to binary 0. Current output of the device. Full scale output current is achieved when all input bits are set to binary 1. Connect 0.1F capacitor to ACOM. Analog Supply to +3.6V). Connect to Analog Ground. Connect to Digital Ground. Digital Supply to +3.6V). Clock Input.


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