|Category||FPGAs/PLDs => PLDs (Programmable Logic Devices) => CPLDs (Computer PLD) => ispLSI 2000VE Family|
|Title||ispLSI 2000VE Family|
|Description||3.3v In-system Programmable Superfast High Density PLD|
|Company||Lattice Semiconductor Corp.|
|Datasheet||Download 2192VE datasheet
|3.3V In-System Programmable SuperFASTTM High Density PLD Features
SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 8000 PLD Gates 96 I/O Pins, Nine or Twelve Dedicated Inputs 192 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic Pinout Compatible with ispLSI 2096V and 2096VE 3.3V LOW VOLTAGE ARCHITECTURE Interfaces with Standard 5V TTL Devices HIGH PERFORMANCE E CMOS TECHNOLOGY fmax = 225MHz* Maximum Operating Frequency tpd = 4.0ns* Propagation Delay Electrically Erasable and Reprogrammable Non-Volatile 100% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power IN-SYSTEM PROGRAMMABLE 3.3V In-System Programmability (ISPTM) Using Boundary Scan Test Access Port (TAP) Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of WiredOR Bus Arbitration Logic Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality Reprogram Soldered Devices for Faster Prototyping 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS Enhanced Pin Locking Capability Three Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity ispDesignEXPERTTM LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING Superior Quality of Results Tightly Integrated with Leading CAE Vendor Tools Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZERTM PC and UNIX Platforms *PreliminaryDescription
The ispLSI is a High Density Programmable Logic Device containing 192 Registers, nine or twelve Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2192VE features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2192VE offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2192VE device is the Generic Logic Block (GLB). The GLBs are labeled A1.. F7 (see Figure 1). There are a total of 48 GLBs in the ispLSI 2192VE device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.comInput Bus Generic Logic Blocks (GLBs) F7 F6 Output Routing Pool (ORP) E7 E6
Output Routing Pool (ORP) Megablock Input Bus
*Note: Dedicated Inputs 2, 5 and 11 are not available with 128-pin packages.
The 2192VE contains 96 I/O cells. Each I/O cell is directly connected to an I/O pin and can be individually programmed be a combinatorial input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4mA or sink 8mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Device pins can be safely driven to 5V signal levels to support mixed-voltage systems. Eight GLBs, 16 I/O cells, two dedicated inputs and an ORP are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each ispLSI 2192VE device contains six Megablocks. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew.
Clocks in the ispLSI 2192VE device are selected using the dedicated clock pins. Three dedicated clock pins or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the ispLSI 2192VE are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the ispDesignEXPERT software tools.
Supply Voltage Vcc.................................. to +5.4V Input Voltage Applied............................... to +5.6V Off-State Output Voltage Applied............ to +5.6V Storage Temperature................................ to 150°C Case Temp. with Power Applied.............. to 125°C Max. Junction Temp. (TJ) with Power Applied... 150°C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
SYMBOL PARAMETER Supply Voltage Input Low Voltage Input High Voltage Commercial + 70°C MIN. 3.0 VSS 0.5 2.0 MAX. 0.8 5.25 UNITS V
SYMBOL PARAMETER Dedicated Input Capacitance I/O Capacitance Clock and Global Output Enable Capacitance TYPICAL 6 10 UNITS pf TEST CONDITIONS VCC = 3.3V, VIN = 0.0V VCC = 3.3V, VI/O = 0.0V VCC = 0.0VPARAMETER Erase/Reprogram Cycles MINIMUM 10,000 MAXIMUM UNITS Cycles
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