|Description||In-system Programmable 3.3v Generic Digital Crosspointtm|
|Company||Lattice Semiconductor Corp.|
|Datasheet||Download 240VA datasheet
IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement "Any Input to Any Output" Routing Fixed HIGH or LOW Output Option for Jumper/DIP Switch Emulation Space-Saving PQFP and BGA Packaging Dedicated IEEE 1149.1-Compliant Boundary Scan Test HIGH PERFORMANCE E2CMOS® TECHNOLOGY 3.3V Core Power Supply 4.5ns Input-to-Output/4.5ns Clock-to-Output Delay 200MHz Maximum Clock Frequency TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels (Individually Programmable) Low-Power: 16.5mA Quiescent Icc 24mA IOL Drive with Programmable Slew Rate Control Option PCI Compatible Drive Capability Schmitt Trigger Inputs for Noise Immunity Electrically Erasable and Reprogrammable Non-Volatile E2CMOS Technology ispGDXVATM OFFERS THE FOLLOWING ADVANTAGES
FLEXIBLE ARCHITECTURE Combinatorial/Latched/Registered Inputs or Outputs Individual I/O Tri-state Control with Polarity Control Dedicated Clock/Clock Enable Input Pins (four) or Programmable Clocks/Clock Enables from I/O Pins (60) Single Level 4:1 Dynamic Path Selection (Tpd = 4.5ns) Programmable Wide-MUX Cascade Feature Supports to 16:1 MUX Programmable Pull-ups, Bus Hold Latch and Open Drain on I/O Pins Outputs Tri-state During Power-up ("Live Insertion" Friendly)
3.3V In-System Programmable Using Boundary Scan Test Access Port (TAP) Change Interconnects in Seconds
DESIGN SUPPORT THROUGH LATTICE'S ispGDX DEVELOPMENT SOFTWARE MS Windows NT / PC-Based or Sun O/S Easy Text-Based Design Entry Automatic Signal Routing Program to 100 ISP Devices Concurrently Simulator Netlist Generation for Easy Board-Level SimulationDescription
The ispGDXVA architecture provides a family of fast, flexible programmable devices to address a variety of system-level digital signal routing and interface requirements including: Multi-Port Multiprocessor Interfaces Wide Data and Address Bus Multiplexing (e.g. 16:1 High-Speed Bus MUX) Programmable Control Signal Routing (e.g. Interrupts, DMAREQs, etc.) Board-Level PCB Signal Routing for Prototyping or Programmable Bus Interfaces The devices feature fast operation, with input-to-output signal delays (Tpd) of 4.5ns and clock-to-output delays of 4.5ns. The architecture of the devices consists of a series of programmable I/O cells interconnected by a Global Routing Pool (GRP). All I/O pin inputs enter the GRP directly or are registered or latched so they can be routed to the required I/O outputs. I/O pin inputs are defined as four sets (A,B,C,D) which have access to the four MUX inputs
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
found in each I/O cell. Each output has individual, programmable I/O tri-state control (OE), output latch clock (CLK), clock enable (CLKEN), and two multiplexer control (MUX0 and MUX1) inputs. Polarity for these signals is programmable for each I/O cell. The MUX0 and MUX1 inputs control a fast 4:1 MUX, allowing dynamic selection up to four signal sources for a given output. A wider 16:1 MUX can be implemented with the MUX expander feature of each I/O and a propagation delay increase of 2.0ns. OE, CLK, CLKEN, and MUX0 and MUX1 inputs can be driven directly from selected sets of I/O pins. Optional dedicated clock input pins give minimum clockto-output delays. CLK and CLKEN share the same set of I/O pins. CLKEN disables the register clock when CLKEN = 0. Through in-system programming, connections between I/O pins and architectural features (latched or registered inputs or outputs, output enable control, etc.) can be defined. In keeping with its data path application focus, the ispGDXVA devices contain no programmable logic arrays. All input pins include Schmitt trigger buffers for noise immunity. These connections are programmed into the device using non-volatile E2CMOS technology. Non-volatile technology means the device configuration is saved even when the power is removed from the device. Table 1. ispGDXV/VA Family Members In addition, there are no pin-to-pin routing constraints for or 1:n signal routing. That is, any I/O pin configured as an input can drive one or more I/O pins configured as outputs. The device pins also have the ability to set outputs to fixed HIGH or LOW logic levels (Jumper or DIP Switch mode). Device outputs are specified for 24mA sink and 12mA source current (at JEDEC LVTTL levels) and can be tied together in parallel for greater drive. On the ispGDXVA, each I/O pin is individually programmable for or 2.5V output levels as described later. Programmable output slew rate control can be defined independently for each I/O pin to reduce overall ground bounce and switching noise. All I/O pins are equipped with IEEE1149.1-compliant Boundary Scan Test circuitry for enhanced testability. In addition, in-system programming is supported through the Test Access Port via a special set of private commands. The ispGDXVA I/Os are designed to withstand "live insertion" system environments. The I/O buffers are disabled during power-up and power-down cycles. When designing for "live insertion," absolute maximum rating conditions for the Vcc and I/O pins must still be met.I/O-CLK / CLKEN Inputs* I/O-MUXsel1 Inputs* I/O-MUXsel2 Inputs* Dedicated Clock Pins**
* The CLK/CLK_EN, OE, MUX0 and MUX1 terminals on each I/O cell can each be assigned 25% of the I/Os. Global clock pins Y1, Y2 and Y3 are multiplexed with CLKEN1, CLKEN2 and CLKEN3 respectively in all devices.
The ispGDXVA architecture is different from traditional PLD architectures, in keeping with its unique application focus. The block diagram is shown below. The programmable interconnect consists of a single Global Routing Pool (GRP). Unlike ispLSI devices, there are no programmable logic arrays on the device. Control signals for OEs, Clocks/Clock Enables and MUX Controls must come from designated sets of I/O pins. The polarity of these signals can be independently programmed in each I/O cell. Each I/O cell drives a unique pin. The OE control for each I/O pin is independent and may be driven via the GRP by one of the designated I/O pins (I/O-OE set). The I/O-OE set consists 25% of the total I/O pins. Boundary Scan test is supported by dedicated registers at each I/O pin. In-system programming is accomplished through the standard Boundary Scan protocol. The various I/O pin sets are also shown in the block diagram below. The B, C, and D I/O pins are grouped together with one group per side.
Each I/O cell contains a 4:1 dynamic MUX controlled by two select lines as well a 4x4 crossbar switch controlled by software for increased routing flexiability (Figure 1). The four data inputs to the MUX (called M1, M2, and M3) come from I/O signals in the GRP and/or adjacent I/O cells. Each MUX data input can access one quarter of the total I/Os. For example, a 240-I/O ispGDXVA, each data input can connect to one of 60 I/O pins. MUX0 and MUX1 can be driven by designated I/O pins called MUXsel1 and MUXsel2. Each MUXsel input covers 25% of the total I/O pins (e.g. 60 out 240). MUX0 and MUX1 can be driven from either or MUXsel2.From MUX Outputs of 2 Adjacent I/O Cells N+1 4x4 Crossbar Switch
Prog. Open Drain 2.5V/3.3V Output Prog. Slew Rate
Inputs Vertical Outputs Horizontal Global Y0-Y3 Reset Global Clocks / Clock_Enables
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