Details, datasheet, quote on part number: MACH211-12JC
DescriptionHigh-performance ee CMOS Programmable Logic
CompanyLattice Semiconductor Corp.
DatasheetDownload MACH211-12JC datasheet
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Features, Applications


High-performance electrically-erasable CMOS PLD families to 128 macrocells to 100 pins in cost-effective PLCC, PQFP and TQFP packages SpeedLockingTM ­ guaranteed fixed timing to 16 product terms Commercial 5/5.5/6/7.5/10/12/15-ns tPD and Industrial 7.5/10/12/14/18-ns tPD Configurable macrocells Programmable polarity Registered or combinatorial outputs Internal and I/O feedback paths D-type or T-type flip-flops Output Enables Choice of clocks for each flip-flop Input registers for MACH 2 family JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available Peripheral component interconnect (PCI) compliant 5/5.5/6/7.5/10/12 ns Safe for mixed supply voltage system designs Bus-FriendlyTM inputs and I/Os reduce risk of unwanted oscillatory outputs Programmable power-down mode results in power savings to 75% Supported by Vantis DesignDirectTM software for rapid logic development Supports HDL design methodologies with results optimized for Vantis Flexibility to adapt to user requirements Software partnerships that ensure customer success Lattice/Vantis and third-party hardware programming support Lattice/VantisPROTM (formerly known as MACHPRO software for in-system programmability support on PCs and Automated Test Equipment Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General

The MACH® & 2 families from Lattice/Vantis offer high-performance, low cost Complex Programmable Logic Devices (CPLDs), addressing the growing need for speed in networking, telecommunications and computing. MACH & 2 devices are available in speeds as fast as 5.0-ns tPD and in densities ranging from to 128 macrocells (Tables 1 and 2). The overall benefits for users include guaranteed high performance for entry-to-mid-level logic needs at a low cost.

Device MACH231 MACH231SP Notes: C = Commercial, I = Industrial 2. -5 speed grade for MACH111 (SP) 5.0 ns tPD 3. -5 speed grade for 5.5 ns tPD -5 C (Note 2) C (Note 2) C (Note 3) C (Note -15 -18

The MACH & 2 families consist of ten devices--five base options, each with a counterpart that includes JTAG-compatible in-system programming (ISP). These devices offer five different densityI/O combinations in Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), and Plastic Leaded Chip Carrier (PLCC) packages from to 100 pins (Table 3). Each MACH & 2 device is PCI compliant and includes other features such as SpeedLocking architecture for guaranteed fixed timing, Bus-Friendly inputs and I/Os, and programmable power-down mode for extra power savings.

Device MACH231SP 44-pin PLCC X 44-pin TQFP 68-pin PLCC 84-pin PLCC 100-pin TQFP 100-pin PQFP

Note: 1. The MACH215, MACH220 and MACH230 are not listed above and not recommended for new designs. However, they are still supported by Lattice/Vantis. For technical or sales support, please call your local Lattice/Vantis sales office or visit our Web site at for more information.

Lattice/Vantis offers software design support for MACH devices in both the MACHXL® and DesignDirect development systems. The DesignDirect development system is the Lattice/Vantis implementation software that includes support for all Lattice/Vantis CPLD, FPGA, and SPLD devices. This system is supported under Windows '95, '98 and NT as well as Sun Solaris and HPUX. DesignDirect software is designed for use with design entry, simulation and verification software from leading-edge tool vendors such as Cadence, Exemplar Logic, Mentor Graphics, Model Technology, Synopsys, Synplicity, Viewlogic and others. It accepts EDIF 2 0 input netlists, generates JEDEC files for Lattice/Vantis PLDs and creates industry-standard EDIF, Verilog, VITAL compliant VHDL and SDF simulation netlists for design verification. DesignDirect software is also available in product configurations that include VHDL and Verilog synthesis from Exemplar Logic and VHDL, Verilog RTL and gate level timing simulation from Model Technology. Schematic capture and ABEL entry, as well as functional simulation, are also provided.


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