Details, datasheet, quote on part number: MACH215-15JC
PartMACH215-15JC
CategoryLogic
DescriptionHigh-density ee CMOS Programmable Logic
CompanyLattice Semiconductor Corp.
DatasheetDownload MACH215-15JC datasheet
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Features, Applications

44 Pins 32 Output Macrocells 32 Input Macrocells Product terms for: Individual flip-flop clock Individual asynchronous reset, preset Individual output enable 12 ns tPD Commercial 14.5 ns tPD Industrial 67 MHz fCNT

38 Inputs with pull-up resistors 32 Outputs 64 Flip-flops For asynchronous and synchronous applications 4 "PAL22RA8" blocks with buried macrocells Pin-compatible with MACH111, MACH210, and MACH211

The is a member of the high-performance EE CMOS MACH device family. This device has approximately three times the capability of the popular PAL20RA10 without loss of speed. This device is designed for use in asynchronous as well as synchronous applications. The MACH215 consists of four PAL blocks interconnected by a programmable switch matrix. The four PAL blocks are essentially "PAL22RA8" structures complete with product-term arrays and programmable macrocells, individual register control product terms, and input registers. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH215 has two kinds of macrocell: output and input. The MACH215 output macrocell provides registered, latched, or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. Each macrocell has its own dedicated clock, asynchronous reset, and asynchronous preset control. The polarity of the clock signal is programmable. All output macrocells can be connected to an I/O cell. The MACH215 has dedicated input macrocells which provide input registers or latches for synchronizing input signals and reducing setup time requirements.


CLK/I = GND I = I/O = VCC Clock or Input Ground Input Input/Output

 

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