Details, datasheet, quote on part number: MACH220-10JC
DescriptionHigh-density ee CMOS Programmable Logic
CompanyLattice Semiconductor Corp.
DatasheetDownload MACH220-10JC datasheet
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Features, Applications

68 Pins 96 Macrocells 10 ns tPD 100 MHz fCNT 56 Inputs with pull-up resistors 48 Outputs

96 Flip-flops; 4 clock choices 8 "PAL26V12" blocks with buried macrocells Pin-compatible with MACH120 and MACH221

The is a member of the high-performance EE CMOS MACH 2 device family. This device has approximately nine times the logic macrocell capability of the popular PAL22V10 without loss of speed. The MACH220 consists of eight PAL blocks interconnected by a programmable switch matrix. The eight PAL blocks are essentially "PAL26V12" structures complete with product-term arrays, and programmable macrocells, including buried macrocells. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH220 has two kinds of macrocell: output and buried. The output macrocell provides registered, latched, or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All output macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. The MACH220 has dedicated buried macrocells which, in addition to the capabilities of the output macrocell, also provide input registers for use in synchronizing signals and reducing setup time requirements.

If you would like to view Block Diagram in full size, please click on the box.
x 52 AND Logic Array and Logic Allocator 26 Switch Matrix

CLK/I = GND I = I/O = VCC Clock or Input Ground Input Input/Output


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