Part  MACH43520JC 
Category  Logic 
Description  Highdensity ee CMOS Programmable Logic 
Company  Lattice Semiconductor Corp. 
Datasheet  Download MACH43520JC datasheet

Quote 
Features, Applications 
s 84 Pins in PLCC s 128 Macrocells 12 ns tPD s 83.3 MHz fCNT s 70 Inputs with pullup resistors s 64 Outputs s 192 Flipflops 128 Macrocell flipflops 64 Input flipflops to 20 product terms per function, with XOR s Flexible clocking Four global clock pins with selectable edges Asynchronous mode available for each macrocell 8 "PAL33V16" blocks s Input and output switch matrices for high routability s Fixed, predictable, deterministic delays s Pin compatible with MACH131, MACH230, and MACH231 The is a member of our highperformance EE CMOS MACH 4 family. This device has approximately twelve times the macrocell capability of the popular PAL22V10, with significant density and functional features that the PAL22V10 does not provide. The MACH435 consists of eight PAL blocks interconnected by a programmable central switch matrix. The central switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fullyconnected PAL blocks. This allows designs to be placed and routed efficiently. Routability is further enhanced by an input switch matrix and an output switch matrix. The input switch matrix provides input signals with alternative paths into the central switch matrix; the output switch matrix provides flexibility in assigning macrocells to I/O pins. The MACH435 has macrocells that can be configured as synchronous or asynchronous. This allows designers to implement both synchronous and asynchronous logic together on the same device. The two types of design can be mixed in any proportion, since the selection on each macrocell affects only that macrocell. to 20 product terms per function can be assigned. It is possible to allocate some product terms away from a macrocell without losing the use of that macrocell for logic generation. The MACH435 macrocell provides either registered or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as Dtype, Ttype, JK, or SR to help reduce the number of product terms used. The flipflop can also be configured as a latch. The register type decision can be made by the designer or by the software. All macrocells can be connected to an I/O cell through the output switch matrix. The output switch matrix makes it possible to make significant design changes while minimizing the risk of pinout changes. I/O24I/031 8 I/O Cells Macrocells OE 16 Output Switch Matrix 8 I/O Cells Macrocells 4 16 Macrocells Output Switch Matrix 8 Output Switch Matrix 4 Output Switch Matrix 16 Macrocells 16 Input Switch Matrix Input Switch Matrix Input Switch Matrix X 90 AND Logic Array and Logic Allocator X 90 AND Logic Array and Logic Allocator 4 8 I/O Cells I/O Cells 8 Clock Generator Clock Generator Clock Generator 16 Input Switch Matrix X 90 AND Logic Array and Logic Allocator I2, I5 Input Switch Matrix Input Switch Matrix Input Switch Matrix X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 Output Switch Matrix 8 I/O Cells 4 8 I/O Cells 16 8 Output Switch Matrix X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 Output Switch Matrix 8 I/O Cells 8 16 Macrocells Clock Generator Clock Generator I/O48I/O55 I/O40I/O47 CLK/I GND I I/O VCC Clock or Input Ground Input Input/Output Supply Voltage 
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