Details, datasheet, quote on part number: MACHLV210-12JC
PartMACHLV210-12JC
CategoryLogic
DescriptionHigh Density ee CMOS Programmable Logic
CompanyLattice Semiconductor Corp.
DatasheetDownload MACHLV210-12JC datasheet
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Features, Applications

s Low-voltage operation, 3.3-V JEDEC compatible VCC +3.6 mA standby current s Patented design allows minimal standby current without speed degradation s Exclusively designed for 3.3-V applications s 44 Pins s 64 Macrocells 12 ns tPD Commercial 18 ns tPD Industrial s 83.3 MHz fCNT

s 38 Bus-Friendly Inputs s 32 Outputs s 64 Flip-flops; 2 clock choices 4 "PAL22V16" blocks with buried macrocells s Pin-, function-, and JEDEC-compatible with MACH210 s Pin-compatible with MACH210, MACH211, and MACH215

The is a member of the highperformance EE CMOS MACH 2 device family. This device has approximately six times the logic macrocell capability of the popular at an equal speed with a lower cost per macrocell. It is architecturally identical to the MACH210, with the addition of I/O pull-up/pull-down resistors and low-voltage, low-power operation. The MACHLV210 provides 3.3-V operation with lowpower CMOS technology. The patented design allows for minimal standby current without speed degradation by limiting the leakage current when signals are not switching. At less than 5 mA maximum standby current, the MACHLV210 is ideal for low-power applications. The MACHLV210 consists of four PAL blocks interconnected by a programmable switch matrix. The four PAL blocks are essentially "PAL22V16" structures complete with product-term arrays and programmable macrocells, including additional buried macrocells. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACHLV210 has two kinds of macrocell: output and buried. The MACHLV210 output macrocell provides registered, latched, or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All output macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. The MACHLV210 has dedicated buried macrocells which, in addition to the capabilities of the output macrocell, also provide input registers or latches for use in synchronizing signals and reducing setup time requirements.

Switch Matrix x 68 AND Logic Array and Logic Allocator
CLK/I = GND I = I/O = VCC Clock or Input Ground Input Input/Output

 

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Some Part number from the same manufacture Lattice Semiconductor Corp.
MACHLV210-15JC High Density ee CMOS Programmable Logic
OR2C04A OR2C04A (5.0V) 11K Usable Gates, 400 Registers, 6K Max User RAM
 
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