|Category||Memory => Flash => Combo|
|Company||Macronix America, Inc.|
|Datasheet||Download MX69F1602 datasheet
16M-BIT [X16] FLASH AND 2M-BIT/4M-BIT [X16] SRAM MIXED MULTI CHIP PACKAGE MEMORY
Supply voltage range: to 3.6V Fast access time: Flash memory:70/90ns SRAM memory:70/85ns Operation temperature range: C - Word write suspend to read - Sector erase suspend to word write - Sector erase suspend to read register report Automatic sector erase, word write and sector lock/ unlock configuration 100,000 minimum erase/program cycles Boot Sector Architecture T = Top Boot Sector B = Bottom Boot Sector Status Register feature for detection of program or erase cycle completion Data protection performance - Sectors to be locked/unlocked Common Flash Interface (CFI) 128-bit Protection Register - 64-bit Unique Device Identifier - 64-bit User-Programmable Latch-up protected to 100mA from to VCC+1V
Word mode only VCCf=VCCQ=2.7V~3.6V for read, erase and program operation VPP=12V for fast production programming Low power consumption - 9mA typical active read current, - 18mA typical program current - 21mA typical erase current - 7uA typical standby current under power saving mode Sector architecture - Sector structure x 2 (boot sectors), x 6 (parameter sectors), x 31 (main sectors) - Top/Bottom Boot Auto Erase and Auto Program - Automatically program and verify data at specified address - Auto sector erase at specified sector Automatic Suspend Enhance
128K wordx16 Bit 256K wordx16 Bit 70mA maximum active current 1uA typical standby current Data retention supply voltage: 2.0V~3.6V Byte data control to Q7) and to Q15)
The MXIC's mixed multi chip memory combines Flash and SRAM into a single package. The mixed multi chip memory operates to 3.6V power supply to allow for simple in-system operation. The Flash memory of mixed multi chip memory manufactured with MXIC's advanced nonvolatile memory technology, the flash memory of mixed multi chip memory is designed to be re-programmed and erased in system or in standard EPROM programmers. The device offers access times of 70ns/90ns, and 7uA typical standby current. Flash memories augment EPROM functionality with incircuit electrical erasure and programming and use a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. Flash memory reliably stores memory contents even after 100,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses to 100 milliamperes on address and data pin from -1V to VCC + 1V. The dedicated VPP pin gives complete data protection when VPP< VPPLK. The Flash contains both a Command User Interface (CUI) and a Write State Machine (WSM). A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for erase, word write and sector lock/ unlock configuration operations. Flash erase automation allows sector erase operation to be executed using an industry-standard two-write command sequence to the CUI. A sector erase operation erases one of the device's 32K-word sectors typically within 1.0s, 4K-word sectors typically within 0.5s independent of other sectors. Each sector can be independently erased minimum 100,000 times. Sector erase suspend mode allows system software to suspend sector erase to read or write data from any other sector. Flash program automation allows program operation to be executed using an industry-standard two-write command sequence to the CUI. Writing memory data is performed in word increments of the device's 32K-word sectors typically within 0.8s and 4K-word sectors typically within 0.1s. Word program suspend mode enables the system to read data or execute code from any other memory array location. The Flash features with individual sectors locking by using a combination of thirty-nine sector lock-bits and WP, to lock and unlock sectors. The Flash status register indicates the status of the WSM when the sector erase, word program or lock configuration operation is done. The Flash power saving mode feature substantially reduces active current when the device is in static mode (addresses not switching). In this mode, the typical ICCS current is 7uA (CMOS) at 3.0V VCC. As CEf and R E SET are at VCC, ICC CMOS standby mode is enabled. When RESET is at GND, the reset mode is enabled which minimize power consumption and provide data write protection. The Flash require a reset time (tPHQV) from RESET switching high until outputs are valid. Similarly, the flash has a wake time (tPHEL) from RESET-high until writes to the CUI are recognized. With RESET at GND, the WSM is reset and the status register is cleared. The 2M-bit SRAM MX69F1602C3T/B is organized by 16-bit. The 4M-bit SRAM MX69F1604C3T/B is organized by 16-bit. The advanced CMOS technology and circuit techniques provide both high speed and low power features of with a typical CMOS standby current of 1uA and maximum access time in 3V operation. The mixed multi chip memory is available x 8mm FBGA Package to suit a variety of design applications.
Feature Vcc Operating Voltage Configuration MX69F1602/1604C3T/B 2.7~3.6V Flash SRAM Fast Access Time Block Architecture Flash 16M:1M Word x16bit MX69F1602C3T/B:128K Word x16bit MX69F1604C3T/B:256K Word x 4K Word Boot x 4K Word Parameter x 32K Word Main Address Pin Flash SRAM Manufacture Code Device ID Code Flash MX69F1602/1604C3T=88C2H MX69F1602/1604C3B=88C3H
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