Details, datasheet, quote on part number: DS89C450-ENL+
PartDS89C450-ENL+
Category
DescriptionUltra-high-speed Flash Microcontrollers
CompanyMaxim Integrated Products
DatasheetDownload DS89C450-ENL+ datasheet
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Features, Applications

The DS89C430, DS89C440, and DS89C450 offer the highest performance available in 8051-compatible microcontrollers. They feature newly designed processor cores that execute instructions to 12 times faster than the original 8051 at the same crystal speed. Typical applications will experience a speed improvement At 1 million instructions per second (MIPS) per megahertz, the microcontrollers achieve 33 MIPS performance from a maximum 33MHz clock rate.

The Ultra-High-Speed Flash Microcontroller Users Guide should be used in conjunction with this data sheet. Download it at www.maxim-ic.com/microcontrollers.

FEATURES

High-Speed 8051 Architecture One Clock-Per-Machine Cycle to 33MHz Operation Single Cycle Instruction in 30ns Optional Variable Length MOVX to Access Fast/Slow Peripherals Dual Data Pointers with Automatic Increment/Decrement and Toggle Select Supports Four Paged Memory-Access Modes On-Chip Memory 16kB/32kB/64kB Flash Memory In-Application Programmable In-System Programmable Through Serial Port 1kB SRAM for MOVX 80C52 Compatible 8051 Pin and Instruction Set Compatible Four Bidirectional, 8-Bit I/O Ports Three 16-Bit Timer Counters 256 Bytes Scratchpad RAM Power-Management Mode Programmable Clock Divider Automatic Hardware and Software Exit ROMSIZE Feature Selects Internal Program Memory Size from to 64kB Allows Access to Entire External Memory Map Dynamically Adjustable by Software Peripheral Features Two Full-Duplex Serial Ports Programmable Watchdog Timer 13 Interrupt Sources (Six External) Five Levels of Interrupt Priority Power-Fail Reset Early Warning Power-Fail Interrupt Electromagnetic Interference (EMI) Reduction

PART DS89C450-ENL DS89C450-ENL+ FLASH MEMORY SIZE 32kB 64kB PIN-PACKAGE 40 PDIP 40 PDIP 44 PLCC 44 PLCC 44 TQFP 44 TQFP 40 PDIP 40 PDIP 44 PLCC 44 PLCC 44 TQFP 44 TQFP 40 PDIP 40 PDIP 44 PLCC 44 PLCC 44 TQFP 44 TQFP

+ Denotes a lead-free/RoHS-compliant device. Complete Selector Guide appears at end of data sheet. Pin Configurations appear at end of data sheet.

APPLICATIONS

Data Logging White Goods Motor Control Magstripe Reader/Scanner Telephones HVAC Vending Gaming Equipment Building Energy Control and Management Programmable Logic Controllers Uninterruptible Power Supplies Building Security and Door Access Control Automotive Text Equipment Consumer Electronics Industrial Control and Automation

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.

Voltage Range on Any Pin Relative Ground.................................................................................-0.3V to (VCC + 0.5V) Voltage Range on VCC Relative to +6.0V Ambient Temperature Range (under to +85C Storage Temperature to +125C Soldering Temperature......................................................................................................See IPC/JEDEC J-STD-020

Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

(VCC to +85C.) (Note 1) PARAMETER Supply Voltage (Notes 2, 3) Power-Fail Warning (Notes 2, 4) Reset Trip Point (Min Operating Voltage) (Notes 3, 4) Supply Current, Active Mode (Note 5) Supply Current, Idle Mode at 33MHz (Note 6) Supply Current, Stop Mode, Bandgap Disabled (Note 7) Supply Current, Stop Mode, Bandgap Enabled (Note 7) Input Low Level (Note 2) Input High Level (Note 2) Input High Level XTAL and RST (Note 2) Output Low Voltage, Port 1 and 3 at IOL = 1.6mA (Note 2) Output Low Voltage, Port 0 and 2, ALE, PSEN at IOL = 3.2mA (Note 2) Output High Voltage, Port 1, 2, and 3, at IOH = -50mA (Notes 2, 8) Output High Voltage, Port 1, 2, and 3 at IOH = -1.5mA (Notes 2, 9) Output High Voltage, Port 1, 2, ALE, PSEN, RD, WR in Bus Mode at IOH = -8mA (Notes 2, 10) Output High Voltage, RST at IOL = -0.4mA (Note 2, 11) Input Low Current, Port 1, 2, and at 0.4V Transition Current from to 0, Port 1, 2, and at 2V (Note 12) Input Leakage Current, Port 0 in I/O Mode and EA (Note 13) Input Current, Port 0 in Bus Mode (Note 14) RST Pulldown Resistance (Note 13) SYMBOL VCC VPFW VRST ICC IIDLE ISTOP ISPBG VIL VIH VOH3 VOH4 IIL ITL IL RRST MIN 4.2 3.95 TYP MAX VCC + 0.3 VCC UNITS mA kW

Note 1: Note 2: Note 3: Specifications to -40C are guaranteed by design and not production tested. All voltages are referenced to ground. The user should note that this part is tested and guaranteed to operate down 4.5V (10%) and that VRST (min) is specified below that point. This indicates that there is a range of voltages [(VMIN to VRST (min)] where the processor's operation is not guaranteed, but the reset trip point has not been reached. This should not be an issue in most applications, but should be considered when proper operation must be maintained at all times. For these applications, it may be desirable to use a more accurate external reset. While the specifications for VPFW and VRST overlap, the design of the hardware makes it so this is not possible. Within the ranges given, there is guaranteed separation between these two voltages. Active current is measured with a 33MHz clock source driving XTAL1, VCC = RST = 5.5V. All other pins are disconnected. Idle mode current is measured with a 33MHz clock source driving XTAL1, VCC = 5.5V, RST at ground. All other pins are disconnected. Stop mode is measured with XTAL and RST grounded, VCC = 5.5V. All other pins are disconnected. RST = 5.5V. This condition mimics the operation of pins in I/O mode. During a 0-to-1 transition, a one shot drives the ports hard for two clock cycles. This measurement reflects a port pin in transition mode. When addressing external memory. Guaranteed by design. Ports 1, 2, and 3 source transition current when pulled down externally. The current reaches its maximum at approximately 2V. RST = 5.5V. Port 0 is floating during reset and when in the logic-high state during I/O mode. This port is a weak address holding latch in bus mode. Peak current occurs near the input transition point of the holding latch at approximately 2V.

Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14:

 

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