|Description||16,777,216-bit CMOS 3.3v-only Flash Memory & 2,097,152-bit CMOS SRAM Stacked-mcp (multi Chip Package)|
|Company||Mitsubishi Electronics America, Inc.|
|Datasheet||Download M6MF16S2AVP datasheet
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BY 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY BY 8-BIT) CMOS STATIC RAM Stacked-MCP (Multi Chip Package) FEATURES Access time (Flash Memory, SRAM) 110ns (Max.) Supply voltage ~ 3.6V Ambient temperature ~ 85°C Package : 48-pin TSOP (Type-I) , 0.4mm lead pitch
DESCRIPTION The MITSUBISHI is a Stacked Muti Chip Package (S-MCP) that contents 16M-bit flash memory and 2M-bit Static RAM a 48-pin TSOP (TYPE-I). 16M-bit Flash memory a 2097152 bytes, 3.3V-only, and high performance non-volatile memory fabricated by CMOS technology for the peripheral circuit and DINOR(DIvided bit-line NOR) architecture for the memory cell. 2M-bit SRAM a 262144 bytes unsynchronous SRAM fabricated by silicon-gate CMOS technology. M6MF16S2AVP is suitable for the application of the mobile-communication-system to reduce both the mount space and weight.
A14 A13 S-WE# S-CE2 A12 F-CE# F-Vcc S-Vcc F-WP2# F-RP# NC F-WP1# S-OE# A17 F-WE# F-OE# S-CE1# F-RY/BY# DQ5 DQ4 F-Vcc F-GND DQ3 S-GND A3 NC
F-Vcc F-GND S-Vcc S-GND A18-A20 DQ0-DQ7 F-CE# F-OE# F-WE# F-WP1#,WP2# F-RP# F-RY/BY# S-CE1#,CE2 S-OE# S-WE#
:Vcc for Flash :GND for Flash :Vcc for SRAM :GND for SRAM :Flash/SRAM common Address :Address for Flash :Data I/O :Flash Chip Enable :Flash Output Enable :Flash Write Enable :Flash Write Protect :Flash Reset Power Down :Flash Ready /Busy :SRAM Chip Enable :SRAM Output Enable :SRAM Write Enabletion. al specifica ge. is not a fin ect to chan bj Notice e ar metric limits Some para
BY 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY BY 8-BIT) CMOS STATIC RAM Stacked-MCP (Multi Chip Package)
A0 256 BYTE PAGE BUFFER 64K BYTE BLOCK0 64K BYTE BLOCK1 64K BYTE BLOCK2 X-DECODER F-VCC F-GND (0V)
CHIP ENABLE INPUT F-CE# OUTPUT ENABLE INPUT F-OE# WRITE ENABLE INPUT F-WE#
RESET/POWER DOWN INPUT F-RP# READY/BUSY OUTPUT F-RY/BY# DQ6 DQ7 DATA INPUTS/OUTPUTS (In common to SRAM)ROW DECODER 262144 WORDS x 8 BITS OUTPUT BUFFER (512 ROWS x 32 BLOCKS) SENSE AMP.
The Flash Memory of M6MF16S2AVP includes on-chip program/erase control circuitry. The Write State Machine (WSM) controls block erase, page (256byte) program operations. Operational modes are selected by the commands written to the Command User Interface (CUI). The Status Register indicates the status of the WSM and when the WSM successfully completes the desired program or block erase operation. A Deep Powerdown mode is enabled when the RP# pin is at GND, minimizing power consumption. Read The Flash Memory of M6MF16S2AVP has three read modes, which accesses to the memory array, the Device Identifier and the Status Register. The appropriate read command are required to be written to the CUI. Upon initial device powerup or after exit from deep powerdown, the Flash Memory automatically resets to read array mode. In the read array mode, low level input to CE# and OE#, high level input to WE# and RP#, and address signals to the address inputs (A0-A20) output the data of the addressed location to the data input/output(D0-D7). Write Writes to the CUI enable reading of memory array data, device identifiers and reading and clearing of the Status Register. they also enable block erase and program. The CUI is written by bringing WE# to low level, while CE# is at low level and OE# is at high level. Addresses and data are latched on the earlier rising edge of WE# and CE#. Standard micro-processor write timings are used. Output Disable When OE# is at VIH, output from the devices is disabled. Data input/output are in a high-impedance(High-Z) state. Standby When CE# is at VIH, the device is in the standby mode and its power consumption is reduced. Data input/output are in a high-impedance(High-Z) state. If the memory is deselected during block erase or program, the internal control circuits remain active and the device consume normal active power until the operation completes. Deep Power-Down When RP# is at VIL, the device is in the deep powerdown mode and its power consumption is substantially low. During read modes, the memory is deselected and the data input/output are in a high-impedance(High-Z) state. After return from powerdown, the CUI is reset to Read Array , and the Status Register is cleared to value 80H. During block erase or program modes, RP# low will abort either operation. Memory array data of the block being altered become invalid. SOFTWARE COMMAND DEFINITIONS The device operations are selected by writing specific software command into the CUI. Read Array Command (FFH) The device is in Read Array mode on initial device powerup and after exit from deep powerdown, or by writing FFH to the CUI. The device remains in Read Array mode until the other commands are written. Read Device Identifier Command (90H) The Device Identifier is read after writing the Read Device Identifier command 90H to the Command User Interface. Following the command write, the manufacturer code and the device code can be read from address 000000H and 000001H, respectively. Read Status Register Command (70H) The Status Register is read after writing the Read Status Register command 70H to the Command User Interface. The contents of Status Register are latched on the later falling edge of OE# or CE#. So CE# or OE# must be toggled every status read. Clear Status Register Command (50H) The Erase Status and Program Status bits are set "1"s by the Write State Machine and can be reset by the Clear Status Register command of 50H. These bits indicates various failure conditions. Block Erase / Confirm Command (20H/D0H) Automated block erase is initiated by writing the Block Erase command of 20H followed by the Confirm command D0H. An address within the block to be erased is required. The WSM executes iterative erase pulse application and erase verify operation. Suspend/Resume Command (B0H/D0H) Writing the Suspend command of B0H during block erase operation interrupts the block erase operation and allows read out from another block of memory. Writing the Suspend command of B0H during program operation interrupts the program operation and allows read out from another block of memory. The device continues to output Status Register data when read, after the Suspend command is written to it. Polling the WSM Status and Suspend Status bits will determine when the erase operation or program operation has been suspended. At this point, writing of the Read Array command to the CUI enables reading data from blocks other than that which is suspended. When the Resume command D0H is written to the CUI, the WSM will continue with the erase or program processes.
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