Details, datasheet, quote on part number: V54C316162VA
PartV54C316162VA
CategoryMemory => DRAM => SDR SDRAM => 4 Mb
DescriptionHigh Performance 3.3v Sdram 2 Banksx512kbitx16: 1mx16
CompanyMosel-Vitelic
DatasheetDownload V54C316162VA datasheet
  

 

Features, Applications

V54C316162VA HIGH PERFORMANCE 3.3 VOLT X 16 SYNCHRONOUS DRAM 2 BANKS X 16
CAS Latency = 3 System Frequency (fCK) Clock Cycle Time (tCK3) Clock Access Time (tAC3)
Features

s 2 banks x 16 organization s High speed data transfer rates to 125 MHz s Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge s Single Pulsed RAS Interface s Dual Data Mask for Byte Control s Dual Banks controlled A11 s Programmable CAS Latency: 3 s Programmable Wrap Sequence: Sequential or Interleave s Programmable Burst Length: and full page for Sequential Type for Interleave Type s Multiple Burst Read with Single Write Operation s Automatic and Controlled Precharge Command s Random Column Address every CLK (1-N Rule) s Suspend Mode and Power Down Mode s Auto Refresh and Self Refresh s Refresh Interval: ms s Available in 50 Pin 400 mil TSOP-II s LVTTL Interface s Single 0.3 V Power Supply

Description

The is a dual bank Synchronous DRAM organized as 2 banks x 16. The V54C316162VA achieves high speed data transfer rates to 125 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the two memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate to 125 MHz is possible depending on burst length, CAS latency and speed grade of the device.

MOSEL-VITELIC MANUFACTURED SYCHRONOUS DRAM FAMILY C = CMOS PROCESS 3.3V, LVTTL, INTERFACE DEVICE PKG NUMBER REVISION LEVEL

SPEED PWR. 12 ns BLANK (NORMAL) T = TSOP-II 2 BANKS 16 (4K REFRESH)

VCC I/O1 I/O2 VSSQ I/O3 I/O4 VCCQ I/O5 I/O6 VSSQ I/O7 I/O8 VCCQ LDQM WE CAS RAS A2 A3 VCC VSS I/O16 I/O15 VSSQ I/O14 I/O13 VCCQ I/O12 I/O11 VSSQ I/O10 I/O9 VCCQ NC UDQM CLK CKE A5 A4 VSS

CLK CKE Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address Inputs Bank Select Data Input/Output Data Mask Power (+3.3V) Ground Power for I/O's (+3.3V) Ground for I/O's Not connected

CS RAS CAS A0A10 A11 (BS) I/O1I/O16 DQM, LDQM, UDQM VCC VSS VCCQ VSSQ NC

Ambient Temperature Under Bias................................... +80 C Storage Temperature (plastic)......... +125 C Input/Output Voltage... -0.5 to Min 4.6) V Voltage Relative to VSS.................. +4.6 V Data Output Current..................................... 50 mA Power dissipation.......................................... 1.0 W

*Note: Operation above Absolute Maximum Ratings can adversely affect device reliability.

Symbol Parameter CI1 CI2 CIO Input Capacitance to A11) Input Capacitance RAS, CAS, WE, CS, CLK, CKE, DQM Output Capacitance (I/O)



 

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