Details, datasheet, quote on part number: V54C31616G2V
PartV54C31616G2V
CategoryMemory => DRAM => SDR SDRAM => 16 Mb
Description166/143 MHZ 3.3v Ultra High Performance 1mx16 Sdram (2 Banks X 512kx16)
CompanyMosel-Vitelic
DatasheetDownload V54C31616G2V datasheet
  

 

Features, Applications

V54C31616G2V 166/143 MHz 3.3 VOLT ULTRA HIGH PERFORMANCE X 16 SDRAM 2 BANKS X 16
Clock Frequency (tCK) Latency Cycle Time (tCK) Access Time (tAC)
Features

s JEDEC Standard 3.3V Power Supply s The V54C31616G2V is ideally suited for high performance graphics peripheral applications s Single Pulsed RAS Interface s Programmable CAS Latency: 3 s All Inputs are sampled at the positive going edge of clock s Programmable Wrap Sequence: Sequential or Interleave s Programmable Burst Length: and Full Page for Sequential and for Interleave s UDQM & LDQM for byte masking s Auto & Self Refresh s 4K Refresh ms s Burst Read with Single Write Operation

Description

The a 16,777,216 bits synchronous high data rate DRAM organized x 524,288 words by 16 bits. The device is designed to comply with JEDEC standards set for synchronous DRAM products, both electrically and mechanically. Synchronous design allows precise cycle control with the system clock. The CAS latency, burst length and burst sequence must be programmed into device prior to access operation.

CLK CKE VSS I/O16 I/O15 VSSQ I/O14 I/O13 VCCQ I/O12 I/O11 VSSQ I/O10 I/O9 VCCQ NC UDQM CLK CKE A5 A4 VSS CS RAS CAS BA I/O1I/O16 LDQM, UDQM VCC VSS VCCQ VSSQ NC Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address Inputs Bank Select Data Input/Output Data Mask Power (+3.3V) Ground Power for I/O's (+3.3V) Ground for I/O's Not connected

MUX Input Buffer Column Decoder UDQM LDQM Memory Array Bank x 16 Output Buffer

Row Address Buffer Column Address Counter Latency 8 Burst Length CLK Programming Register A0-A10, BA Column Address Buffer Row Addresses


 

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Some Part number from the same manufacture Mosel-Vitelic
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