Details, datasheet, quote on part number: V54C31732G2V-7
PartV54C31732G2V-7
CategoryMemory => DRAM => SDR SDRAM => 16 Mb
DescriptionHigh Performance 166/143 MHZ 3.3v Enhanced Graphics 512k X 32 Sdram 2 Banksx256kbitx32
CompanyMosel-Vitelic
DatasheetDownload V54C31732G2V-7 datasheet
  

 

Features, Applications

V54C31732G2V HIGH PERFORMANCE 166/143 MHz 3.3 VOLT ENHANCED GRAPHICS X 32 SDRAM 2 BANKS X 32
Clock Frequency (tCK) Latency Cycle Time (tCK) Access Time (tAC)
Features

JEDEC Standard 3.3V Power Supply Specially screened for graphics applications Single Pulsed RAS Interface Programmable CAS Latency: 2, 3 All Inputs are sampled at the positive going edge of clock Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: and Full Page for Sequential and for Interleave DQM 0-3 for Byte Masking Auto & Self Refresh 2K Refresh Cycles/32 ms Special Mode Registers One Color Register Burst Read with Single Write Operation Block Write (8 Columns)

Description

The a 33,554,432 bits synchronous high data rate DRAM organized x 262,144 words by 32 bits. The device is designed to comply with JEDEC standards set for synchronous DRAM products, both electrically and mechanically. Synchronous design allows precise cycle control with the system clock. The CAS latency, burst length and burst sequence must be programmed into device prior to access operation. In addition, it features block write and masked block write functions by making a programmable mode register and special mode register, the system can select modes to maximize its performance.

DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ DQM3 DQM1 CLK CKE DSF NC A9/AP

DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DQM2 WE CAS RAS BA A8

Color Register Input Buffer Column Decoder DQMi Memory Array Bank x 32 Output Buffer

Row Address Buffer Column Address Counter Latency 8 Burst Length CLK Programming Register A0-A9, BA Column Address Buffer Row Addresses


 

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