Details, datasheet, quote on part number: V54C3256164VALT6
PartV54C3256164VALT6
CategoryMemory => DRAM => SDR SDRAM
DescriptionHigh Performance 3.3 Volt 16m X 16 Synchronous DRAM 4 Banks X 4mbit X 16
CompanyMosel-Vitelic
DatasheetDownload V54C3256164VALT6 datasheet
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Features, Applications

V54C3256164V HIGH PERFORMANCE 3.3 VOLT X 16 SYNCHRONOUS DRAM 4 BANKS X 16

-75 System Frequency (fCK) Clock Cycle Time (tCK3) Clock Access Time (tAC3) CAS Latency = 3 Clock Cycle Time (tCK2) Clock Access Time (tAC2) CAS Latency 6 ns

Features

s 4 banks x 16 organization s High speed data transfer rates to 133 MHz s Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge s Single Pulsed RAS Interface s Data Mask for byte Control s Four Banks controlled BA1 s Programmable CAS Latency: 3 s Programmable Wrap Sequence: Sequential or Interleave s Programmable Burst Length: and full page for Sequential Type for Interleave Type s Multiple Burst Read with Single Write Operation s Automatic and Controlled Precharge Command s Random Column Address every CLK (1-N Rule) s Suspend Mode and Power Down Mode s Auto Refresh and Self Refresh s Refresh Interval: ms s Available in 54 Pin 400 mil TSOP-II s LVTTL Interface s Single 0.3 V Power Supply s -75 parts for PC133 3-3-3 operation s -8PC parts for PC100 2-2-2 operation s -8 parts for PC100 3-2-2 operation

Description

The is a four bank Synchronous DRAM organized as 4 banks x 16. The V54C3256164V achieves high speed data transfer rates to 133 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate to 133 MHz is possible depending on burst length, CAS latency and speed grade of the device.

VCC I/O1 VCCQ I/O2 I/O3 VSSQ I/O4 I/O5 VCCQ I/O6 I/O7 VSSQ I/O8 VCC LDQM WE CAS RAS A2 A3 VCC VSS I/O16 VSSQ I/O15 I/O14 VCCQ I/O13 I/O12 VSSQ I/O11 I/O10 VCCQ I/O9 VSS NC UDQM CLK CKE A5 A4 VSS

CLK CKE Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address Inputs Bank Select Data Input/Output Data Mask Power (+3.3V) Ground Power for I/O's (+3.3V) Ground for I/O's Not connected

Symbol Parameter CI1 CI2 CIO CCLK Input Capacitance to A11) Input Capacitance RAS, CAS, WE, CS, CLK, CKE, DQM Output Capacitance (I/O) Input Capacitance (CLK)


 

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