Details, datasheet, quote on part number: V54C3256404VA
PartV54C3256404VA
CategoryMemory => DRAM => SDR SDRAM => 256 Mb
DescriptionHigh Performance 133/125 MHZ 3.3 Volt 64M X 4 Synchronous DRAM
CompanyMosel-Vitelic
DatasheetDownload V54C3256404VA datasheet
  

 

Features, Applications

V54C3256404VA HIGH PERFORMANCE 3.3 VOLT X 4 SYNCHRONOUS DRAM 4 BANKS X 4

-7 System Frequency (fCK) Clock Cycle Time (tCK3) Clock Access Time (tAC3) CAS Latency = 3 Clock Cycle Time (tCK2) Clock Access Time (tAC2) CAS Latency 6 ns

Features

I 4 banks x 4 organization I High speed data transfer rates to 143 MHz I Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge I Single Pulsed RAS Interface I Data Mask for Read/Write Control I Four Banks controlled BA1 I Programmable CAS Latency: 3 I Programmable Wrap Sequence: Sequential or Interleave I Programmable Burst Length: full page (optional) for Sequential Type for Interleave Type I Multiple Burst Read with Single Write Operation I Automatic and Controlled Precharge Command I Random Column Address every CLK (1-N Rule) I Suspend Mode and Power Down Mode I Auto Refresh and Self Refresh I Refresh Interval: ms I Available in 54 Pin 400 mil TSOP-II I LVTTL Interface I Single ±0.3 V Power Supply I -7 parts for PC133 3-3-3 operation I -8PC parts for PC100 2-2-2 operation I -8 parts for PC100 3-2-2 operation

Description

The is a four bank Synchronous DRAM organized as 4 banks x 4. The V54C3256404VA achieves high speed data transfer rates to 143 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate to 143 MHz is possible depending on burst length, CAS latency and speed grade of the device.

CLK CKE VSS NC VSSQ NC I/O4 VCCQ NC VSSQ NC I/O3 VCCQ NC VSS NC DQM CLK CKE A5 A4 VSS CS RAS CAS BA1 I/O1­I/O4 DQM VCC VSS VCCQ VSSQ NC Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address Inputs Bank Select Data Input/Output Data Mask Power (+3.3V) Ground Power for I/O's (+3.3V) Ground for I/O's Not connected

Symbol Parameter CI1 CI2 CIO CCLK Input Capacitance to A11) Input Capacitance RAS, CAS, WE, CS, CLK, CKE, DQM Output Capacitance (I/O) Input Capacitance (CLK)

Operating temperature to 70°C Storage temperature to 150°C Input/output (VCC+0.3) V Power supply 4.6 V Power dissipation1 W Data out current (short circuit)50 mA

*Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.


 

Some Part number from the same manufacture Mosel-Vitelic
V54C3256404VB 256Mbit Sdram 3.3 Volt, Tsop ii / Soc / Wbga Package 16M X 16, 32M X 8, 64M X 4
V54C3256404VC 256Mbit Sdram 3.3 Volt, Tsop ii / Truecsp Package 16M X 16, 32M X 8, 64M X 4
V54C3256404VS 256Mbit Sdram 3.3 Volt, Tsop ii / Soc / Wbga Package 16M X 16, 32M X 8, 64M X 4
V54C3256404VT 256Mbit Sdram 3.3 Volt, Tsop ii / Truecsp Package 16M X 16, 32M X 8, 64M X 4
V54C3256804V High Performance 3.3 Volt 32m X 8 Synchronous DRAM 4 Banks X 8mbit X 8
V54C3256804VA High Performance 133/125 MHZ 3.3 Volt 32M X 8 Synchronous DRAM
V54C3256804VB 256Mbit Sdram 3.3 Volt, Tsop ii / Soc / Wbga Package 16M X 16, 32M X 8, 64M X 4
V54C3256804VC 256Mbit Sdram 3.3 Volt, Tsop ii / Truecsp Package 16M X 16, 32M X 8, 64M X 4
V54C3256804VS 256Mbit Sdram 3.3 Volt, Tsop ii / Soc / Wbga Package 16M X 16, 32M X 8, 64M X 4
V54C3256804VT 256Mbit Sdram 3.3 Volt, Tsop ii / Truecsp Package 16M X 16, 32M X 8, 64M X 4
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