Details, datasheet, quote on part number: V54C3256404VBT6
PartV54C3256404VBT6
CategoryMemory => DRAM => SDR SDRAM => 256 Mb
Description256Mbit Sdram 3.3 Volt, Tsop ii / Soc / Wbga Package 16M X 16, 32M X 8, 64M X 4
CompanyMosel-Vitelic
DatasheetDownload V54C3256404VBT6 datasheet
  

 

Features, Applications

6 System Frequency (fCK) Clock Cycle Time (tCK3) Clock Access Time (tAC3) CAS Latency = 3 Clock Access Time (tAC2) CAS Latency 2 166 MHz 5.4 ns

Features

4 banks x 16 organization 4 banks x 8 organization 4 banks x 4 organization High speed data transfer rates to 166 MHz Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge Single Pulsed RAS Interface Data Mask for Read/Write Control Four Banks controlled & BA1 Programmable CAS Latency: 2, 3 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: for Sequential Type for Interleave Type Multiple Burst Read with Single Write Operation Automatic and Controlled Precharge Command Random Column Address every CLK (1-N Rule) Power Down Mode Auto Refresh and Self Refresh Interval: cycles/64 ms Available in 54 Pin TSOP II, 60 Ball WBGA and SOC BGA LVTTL Interface Single 0.3 V Power Supply

Description

The is a four bank Synchronous DRAM organized as 4 banks 16, 4 banks or 4 banks x 4. The V54C3256(16/80/40)4V(T/S/B) achieves high speed data transfer rates to 166 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate to 166 MHz is possible depending on burst length, CAS latency and speed grade of the device.

Mosel Vitelic Manufactured SYNCHRONOUS DRAM FAMILY Device Number Special Feature Speed 8 ns TSOP Component Package L=Low Power 4 Banks V=LVTTL Component Rev Level A=0.17um B=0.14um

CLK CKE Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address Inputs Bank Select Data Input/Output Data Mask Power (+3.3V) Ground Power for I/O's (+3.3V) Ground for I/O's Not connected


 

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