Details, datasheet, quote on part number: MC10212FN
PartMC10212FN
CategoryLogic
DescriptionHigh Speed Dual 3-input/3-output Or/nOR GATE
CompanyMotorola Semiconductor Products
DatasheetDownload MC10212FN datasheet
Quote
Find where to buy
 
  

 

Features, Applications

The MC10212 is designed to drive up to six transmission lines simul­ taneously. The multiple outputs of this device also allow the wire "OR"­ing of several levels of gating for minimization of gate and package count. The ability to control three parallel lines with minimum propagation delay from a single point makes the MC10212 particularly useful in clock distribution applications where minimum clock skew is desired.

L SUFFIX CERAMIC PACKAGE CASE 620­10 P SUFFIX PLASTIC PACKAGE CASE 648­08 FN SUFFIX PLCC CASE 775­02

Pin assignment is for Dual­in­Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6­11 of the Motorola MECL Data Book (DL122/D).

Characteristic Power Supply Drain Current Input Current

* Individually test each input using the pin connections shown. Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50­ohm resistor to ­2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.


 

Related products with the same datasheet
MC10212L
MC10212P
Some Part number from the same manufacture Motorola Semiconductor Products
MC10212L High Speed Dual 3-input/3-output Or/nOR GATE
MC10216FN High Speed Triple Line Receiver
MC10216L
MC10216P
MC10231FN High Speed Dual Type D Master-slave Flip-flop
MC10231L
MC10231P
MC10319
MC10322
MC10324
MC10E016FN 8-bit Synchronous Binary up Counter
MC10E101FN Quad 4-input Or/nOR GATE
MC10E104FN Quad 2-input And/hand Gate
MC10E107FN Quint 2-input Xor/xnOR GATE
MC10E111FN 1:9 Differential Clock Driver
MC10E112FN Quad Driver
MC10E116FN Quint Differential Line Receiver
MC10E122FN 9-bit Buffer
MC10E131FN 4-bit D Flip-flop
MC10E136FN 6-bit Universal Up/down Counter
MC10E137FN 8-bit Ripple Counter

68HC05L5 : CISC->68XX Family Microcontroller

MC14522BCP : Dual 1.1 GHZ PLL Frequency Synthesizer

MC68HC000P10 : Microprocessor, Sixteen 32-bit Data And Address Registers, 16-Mbyte Direct Addressing Range, Memory-mapped Input/output (I/O), 14 Addressing Modes, 10MHz

MC74F827DW : 10-bit Buffers/line Drivers ( With 3-state Outputs )

MC7924BT : 1.0 a Negative Voltage Regulators

PC33880DWBR2 : Configurable Octal Serial Switch With Serial Peripheral Interface I/o

DSP56374 : The DSP56374 is designed to support a multitude of digital signal processing applications requiring a lot of horsepower in a small package. While the DSP56374 is designed with flexibility and thus is versatile in the types of applications it can support, it does include a powerful set of aud

MC8641VU1000J : Integrated Host Processor Hardware Specifications

Same catergory

74ACT11175DW : D-Type Flip-Flops. ti 74ACT11175, Quadruple D-type Flip-flops With Clear.

74ALVC16373 : Low Voltage 16-Bit Transparent Latch With 3.6V Tolerant Inputs And Outputs.

74LVCH16827A : 3.3V CMOS 20-BIT Buffer With 5 Volt Tolerant I/o And Bus-hold. 3.3V CMOS 20-BIT BUFFER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD Typical tSK(o) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method > 200V using machine model = 0) VCC ± 0.3V, Normal Range VCC to 3.6V, Extended Range CMOS power levels (0.4µ W typ. static) All inputs, outputs, and I/O are 5V tolerant Supports hot insertion Available in SSOP,.

CD4055B : CMOS/BiCMOS->4000 Family. CMOS Liquid-crystal Display Drivers. Data sheet acquired from Harris Semiconductor SCHS048A ­ Revised March 2002 The CD4054B-, CD4055B-, and CD4056B-series types are available in 16-lead ceramic dual-in-line packages (D and F suffixes), 16-lead plastic packages (E suffix), 16-lead small-outline package (NSR suffix), and in chip form (H suffix). .

CD54HC597 : CMOS/BiCMOS->HC/HCT Family. High Speed CMOS Logic 8-bit Shift Register With Input Storage.

CD74AC238M96 : Decoders. ti CD74AC238, 3-Line to 8-Line Non-inverting Decoder/demultiplexer.

CD74AC540 : CMOS/BiCMOS->AC/ACT Family. Octal Buffer/line Drivers, 3-state. Data sheet acquired from Harris Semiconductor SCHS285A ­ Revised November 1999 The CD54/74AC540, -541, and CD54/74ACT540, -541 octal buffer/line drivers use the RCA ADVANCED CMOS technology. The CD54/74AC/ACT540 are inverting 3-state buffers having two active-LOW output enables. The CD54/74AC/ACT541 are non-inverting 3-state buffers having two active-LOW.

CD74ACT280E : Parity Generators and Checkers. ti CD74ACT280, 9-Bit Odd/even Parity Generator/checker.

DM74LS645 : Bus Oriented Circuits. Octal 3-STATE Bus Transceiver. These octal bus transceivers are designed for asynchronous two-way communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction control (DIR) input. The enable input (G) can be used to disable the device so that the buses are effectively isolated. s Bi-directional.

M54HCT14 : Hex Schmitt Inverter. HIGH SPEED tPD 16 ns (TYP.) AT VCC 5 V LOW POWER DISSIPATION ICC 1 µA (MAX.) 25 °C HIGH NOISE IMMUNITY 0.7 V (TYP.) AT VCC 5 V OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL PIN AND FUNCTION COMPATIBLE WITH 54/74LS14 The is a high speed CMOS HEX SCHMITT INVERTER fabricated.

M74HC166 : HC/HCT->High Speed CMOS. 8 Bit Piso Shift Register. HIGH SPEED : fMAX = 63 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 166 The is an high speed CMOS 8 BIT PISO.

MC74ACT00 : CMOS/BiCMOS->AC/ACT Family. Quad 2 Input NAND Gate. Output Drive Capability: $24 mA Operating Voltage Range: 5.5 ACT00 Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 32 FETs A = Assembly Location L = Wafer Lot Y = Year W = Work Week Figure 2. Pinout: 14­Lead Packages (Top View) FUNCTION TABLE See detailed.

SN54HCT273 : Octal D-type Flip-flops With Clear. Inputs Are TTL-Voltage Compatible Contain Eight D-Type Flip-Flops Direct Clear Input Applications Include: ­ Buffer/Storage Registers ­ Shift Registers ­ Pattern Generators Package Options Include Plastic Small-Outline (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs These devices.

SN74ACT3622 : CMOS/BiCMOS->AC/ACT Family. Clocked Bidirectional Fifo: 256x36x2. Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent Clocked FIFOs Buffering Data in Opposite Directions Mailbox-Bypass Register for Each FIFO Programmable Almost-Full and Almost-Empty Flags Microprocessor Interface Control Logic IRA, ORA, AEA, and AFA Flags Synchronized by CLKA IRB, ORB, AEB, and AFB Flags Synchronized by CLKB.

SN74ALS575ADW : D-Type (3-State) Flip-Flops. ti SN74ALS575A, Octal D-type Edge-triggered Flip-flops With 3-State Outputs.

SN74ALVC10DGV : Triple 3-input Positive-nand Gate. EPIC TM (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model = 200 pF, = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline (D), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages This.

SN74AUC1G02DBVR : Single Gates. ti SN74AUC1G02, Single 2-Input Positive-nOR GATE. NanoStar and NanoFree Packages Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub 1-V Operable Max tpd 1.8 V Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD.

SN74LVC07A : CMOS/BiCMOS->LVC/ALVC/VCX Family->Low Voltage. Hex Buffers/drivers With Open-drain Outputs.

A2F200M3F-FGH256I : IC,FPGA,4608-CELL,CMOS,BGA,256PIN,PLASTIC. s: Device Type: FPGA. Hard 100 MHz 32-Bit ARM ­ 1.25 DMIPS/MHz Throughput from Zero Wait State Memory ­ Memory Protection Unit (MPU) ­ Single Cycle Multiplication, Hardware Divide ­ JTAG Debug (4 wires), Serial Wire Debug (SWD, 2 wires), and Single Wire Viewer (SWV) Interfaces Internal Memory ­ Embedded Nonvolatile Flash Memory (eNVM), 128 Kbytes to 512 Kbytes ­ Embedded.

100370FC : 100K SERIES, OTHER DECODER/DRIVER, CONFIGURABLE OUTPUT, CQFP24. s: Function: Decoder ; Package Type: CERPACK-24 ; Logic Family: ECL ; Number of Pins: 24 ; Propagation Delay: 2.1 ns ; Operating Temperature: 0 to 85 C (32 to 185 F).

 
0-C     D-L     M-R     S-Z