|Description||Integrated Coldfire Version 4 Microcontroller|
|Company||Motorola Semiconductor Products|
|Datasheet||Download MCF5483 datasheet
The is a highly-integrated implementation of the ColdFireŽ family of reduced instruction set computing (RISC) microprocessors. This document describes pertinent electrical and physical characteristics of the MCF548x family: the MCF5483, MCF5484, and MCF5485. This document contains the following topics: Topic Section 1.1, "MCF548x Family Overview" Section 1.2, "MCF548x Block Diagram" Section 1.3, "MCF548x Family Products" Section 1.4, "MCF548x Family Features" Section 1.5, "Signal Description" Section 1.6, "Chip Configuration" Section 1.7, "Design Recommendations" Section 1.8, "MCF5485/5484 Pinout" Section 1.9, "MCF5483/5482 Pinout" Section 1.10, "MCF5481/5480 Pinout" Section 1.11, "Mechanicals" Section 1.12, "Ordering Information" Section 1.13, "Device/Family Documentation List" Section 1.14, "Document Revision History" Appendix A, "Preliminary Electrical Characteristics" Page
To locate any published errata or updates for this document, refer to the web site at http://motorola.com/semiconductors.
The MCF548x family is based on the ColdFire V4e core, a complex which comprises the ColdFire V4 central processor unit (CPU), an enhanced multiply-accumulate unit (EMAC), a memory management unit (MMU), a double-precision floating point unit (FPU) conforming to standard IEEE-754, and controllers for caches and local data memories. The MCF548x family is capable of performing at an operating frequency to 200 MHz or 308 MIPS (Dhrystone 2.1).
To maximize throughput, the MCF548x family incorporates three independent external bus interfaces: 1. The general-purpose local bus (FlexBus) is used for system boot memories and simple peripherals and has up to six chip selects. 2. Program code and data can be stored in SDRAM connected to a dedicated 32-bit double data rate (DDR) bus that can run up to one half of the CPU core frequency. The glueless DDR SDRAM controller handles all address multiplexing, input and output strobe timing, and memory bus clock generation. A 32-bit PCI bus compliant with the version 2.2 specification and running at a typical frequency of 33 MHz or 66 MHz supports peripherals that require high bandwidth, the ability to arbitrate for bus mastership, and access to internal MCF548x memory resources. The MCF548x family provides substantial communications functionality by integrating the following connectivity peripherals:
Up to two 10/100 Mbps fast Ethernet controllers (FECs) An optional USB 2.0 device (slave) module with seven endpoints and an integrated transceiver Up to four UART/USART/IRDA/modem programmable serial controllers (PSCs) A DMA serial peripheral interface (DSPI) An inter-integrated circuit (I2CTM) bus controller Two controller area network 2.0B (FlexCAN) interfaces with 16 message buffers each
Additionally, the MCF548x provides hardware support for a range of Internet security standards with an optional bus-mastering cryptography accelerator. This module incorporates units to speed DES/3DES and AES block ciphers, the RC4 stream cipher, bulk data hashing (MD5/SHA-1/SHA-256/HMAC), and random number generation. Hardware acceleration of these functions is critical to avoiding the throughput bottlenecks associated with software-only implementations of SSH, SSL/TLS, IPsec, SRTP, WEP, and other security standards. The incorporation of cryptography acceleration makes the MCF548x family a compelling solution for a wide range of office automation, industrial control, and SOHO networking devices that must have the ability to securely transmit critical equipment control information across typically insecure Ethernet data networks. Additional features of MCF548x products include a watchdog timer, two 32-bit slice timers for RTOS scheduling and alarm functionality, up to four 32-bit general-purpose timers with capture, compare, and pulse width modulation capability, a multisource vectored interrupt controller, a phase-locked loop (PLL) to generate the system clock, 32 Kbytes of SRAM for high-speed local data storage, and multiple general-purpose I/O ports. To manage current consumption, MCF548x products provide chip-wide internal clock gating control on a per module basis under software control. With on-chip support for multiple common communications interfaces, MCF548x products require only the addition of memories and certain physical layer transceivers to be cost-effective system solutions for many applications, such as industrial routers, high-end POS terminals, building automation systems, and process control equipment. MCF548x products require four supply voltages: 1.5V for the high-performance, low power, internal core logic, 2.5V for the DDR SDRAM bus interface, 1.25V for the DDR SDRAM VREF, and 3.3V for all other I/O functionality, including the PCI and FlexBus interfaces.
MCF548x Integrated Microprocessor Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product, Go to: www.freescale.comFigure 1 shows a top-level block diagram of the MCF548x products.
ColdFire V4e Core FPU, MMU EMAC 32K D-cache 32K I-cache
Interrupt Controller Watchdog Timer Slice Timers x 2
*Available MCF5484, MCF5483, and MCF5482 devices. **Available MCF5484, MCF5481, and MCF5480 devices. ***Available MCF5485, MCF5483, and MCF5481 devices.
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