|Category||Communication => Freq/Signal Converters/Generators|
|Company||Motorola Semiconductor Products|
|Datasheet||Download MCH12140 datasheet
The is a phase frequency-detector intended for phase-locked loop applications which require a minimum amount of phase and frequency difference at lock. When used in conjunction with the or MC12149 VCO, a high bandwidth PLL can be realized. The device is functionally compatible with the MC12040 phase-frequency detector, however the MOSAICTM III process is used to push the maximum frequency to 800 MHz and significantly reduce the dead zone of the detector. When the Reference (R) and VCO (V) inputs are unequal in frequency and/or phase, the differential UP (U) and DOWN (D) outputs will provide pulse streams which when subtracted and integrated provide an error voltage for control of a VCO. The device is packaged in a small outline, surface mount 8-lead SOIC package. There are two versions of the device to provide I/O compatibility to the two existing ECL standards. The MCH12140 is compatible with MECL10HTM logic levels while the MCK12140 is compatible to 100K ECL logic levels. This device can also be used +5.0 V systems. Please refer to Motorola Application Note AN1406/D, "Designing with PECL (ECL at +5.0 V)" for more information.
800 MHz Typical Bandwidth Small Outline 8-Lead SOIC Package 75 k Internal Input Pulldown Resistors >1000 V ESD ProtectionFor proper operation, the input edge rate of the R and V inputs should be less than 5ns.
NOTE: * This is not strictly a functional table; i.e., it does not cover all possible modes of operation. However, it gives a sufficient number of tests to ensure that the device will function properly.HSERIES DC CHARACTERISTICS (VEE = VEE(min) VEE(max); VCC = GND1, unless otherwise noted.)
40°C Characteristic Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltge Input LOW Current
1. 10H circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been established. The circuit in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. Outputs are terminated through a 50 resistor to 2.0V except where otherwise specified on the individual data sheets.KSERIES DC CHARACTERISTICS (VEE = VEE(min) VEE(max); VCC = GND1, unless otherwise noted.)
40°C Characteristic Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltge Input LOW Current
to 70°C Max Min Typ 955 1705 Max Unit mV µA VIN = VIL(max) Condition VIN = VIH(max) or VIL(min) VIN = VIH(min) or VIL(max)
1. This table replaces the three tables traditionally seen in ECL 100K data books. The same DC parameter values at VEE = 4.5V now apply across the full VEE range to 5.5V. Outputs are terminated through a 50 resistor to 2.0V except where otherwise specified on the individual data sheets.
Characteristic Power Supply (VCC = 0V) Input Voltage (VCC = 0V) Output Current Continuous Surge Symbol VEE VI Iout TA VEE Rating to 4.2 Unit VDC °C V
NOTES: 1. Absolute maximum rating, beyond which, device life may be impaired, unless otherwise specified on an individual data sheet. 2. Parametric values specified at: HSeries: 5.50 V KSeries: V 3. ESD data available upon request.DC CHARACTERISTICS (VEE = VEE(min) VEE(max); VCC = GND, unless otherwise noted.)
AC CHARACTERISTICS (VEE = VEE(min) VEE(max); VCC = GND, unless otherwise noted.)
The is a high speed digital circuit used as a phase comparator in an analog phase-locked loop. The device determines the "lead" or "lag" phase relationship and time difference between the leading edges of a VCO (V) signal and a Reference (R) input. Since these edges occur only once per cycle, the detector has a range of ±2 radians. The operation of the 12140 can best be described using the plots of Figure 1. Figure 1 plots the average value U, D and the difference between U and D versus the phase difference between the V and R inputs. There are four potential relationships between V and R: R lags or leads V and the frequency R is less than or greater than the frequency of V. Under these four conditions the 12140 will function as follows: Figure 1. Average Output Voltage versus Phase Difference
R lags V in phase When the R and V inputs are equal in frequency and the phase of R lags that of V the U output will stay HIGH while the D output will pulse from HIGH to LOW. The magnitude of the pulse will be proportional to the phase difference between the V and R inputs reaching a minimum 50% duty cycle under a 180° out of phase condition. The signal on D indicates to the VCO to decrease in frequency to bring the loop into lock. V frequency > R frequency When the frequency V is greater than that of R the 12140 behaves in a simlar fashion as above. Again the signal on D indicates that the VCO frequency must be decreased to bring the loop into lock. R leads V in phase When the R and V inputs are equal in frequency and the phase of R leads that of V the D output will stay HIGH while the U output pulses from HIGH to LOW. The magnitude of the pulse will be proportional to the phase difference between the V and R inputs reaching a minimum 50% duty cycle under a 180° out of phase condition. The signal on U indicates to the VCO to increase in frequency to bring the loop into lock. V frequency < R frequency When the frequency V is less than that of R the 12140 behaves in a simlar fashion as above. Again the signal on U indicates that the VCO frequency must be decreased to bring the loop into lock. From Figure 1 when V and R are at the same frequency and in phase the value D is zero thus providing a zero error voltage to the VCO. This situation indicates the loop is in lock and the 12140 action will maintain the loop in its locked state.
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