Details, datasheet, quote on part number: MCM101525
Description2m X 2 Bit Fast Static Random Access Memory With Ecl I/o
CompanyMotorola Semiconductor Products
DatasheetDownload MCM101525 datasheet
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Features, Applications

x 2 Bit Fast Static Random Access Memory with ECL I/O

The a 4,194,304 bit static random access memory organized as 2,097,152 words of 2 bits. This device features complementary outputs. This circuit is fabricated using high performance silicon­gate BiCMOS technology. Asynchronous design eliminates the need for external clocks or timing strobes. The MCM101525 is available a 400 mil, 36 lead TAB. Fast Access Times: 12, 15 ns Equal Address and Chip Select Access Time Power Operation: 195 mA Maximum, Active AC BLOCK DIAGRAM


­ A20. Address Inputs S. Chip Select ­ Q1. Data Output NC. No Connection VCC. Ground W. Write Enable ­ D1. Data Input Q0 and Q1. Complementary Data Out VEE. Power Supply

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

Operation Not Enabled Read Write Data X Output L Q/Q L Current IEE

Rating VEE Pin Potential (to Ground) Voltage Relative to VCC for Any Pin Except VEE Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Symbol VEE Vin, Vout Iout PD Tbias TJ Value + 0.5 VEE + 60 Unit W °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high impedance circuits. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

Storage Temperature Plastic Tstg 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.


Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Low Current Input High Current Chip Select Input Low Current Operating Power Supply Current: tAVAV 20 ns (All Outputs Open)* Quiescent Power Supply Current: = 0 MHz (Outputs Open) Voltage Compensation (VOH) Voltage Compensation (VOL) * Address Increment Symbol VEE VIH VIL VOH VOL IIL IIH IIL(CS) IEE IEEQ VOH/VEE VOL/VEE Min Typ ­ 5.2 Max Unit µA mA

Parameter Output Rise Time Output Fall Time Symbol tr tf Test Condition to 80% Min 0.5 Typ 1.0 Max 1.5 Unit ns

CAPACITANCE = 1.0 MHz, = 25°C, Periodically Sampled Rather Than 100% Tested)

Parameter Input Capacitance Output Capacitance Address and Data Q, Q Symbol Cin Cck Cout Typ 3.5 4 Max 7 8 Unit pF

Input Pulse Levels. 0.9 V (See Figure 1) Input Rise/Fall Time. 1 ns Input Timing Measurement Reference Level. 50% Output Timing Measurement Reference Level. VOH 1165 mV VOL 1475 mV Output Load (AC Test Circuit). See Figure 2

MCM101525­12 Parameter Read Cycle Time Address Access Time Chip Select Access Time Select High to Output Low Output Hold from Address Change Power Up Time Symbol tAVAV tAVQV tSLQV tSHQL tAXQX tSLIEEH Min Max 8 MCM101525­15 Min Max 15 9 Unit 4 6 Notes 2, 3

Power Down Time tSHIEEL 12 15 NOTES: W is high for read cycle. 2. Product sensitivites to noise require proper grounding and decoupling of power supplies during read and write cycles. 3. All read cycle timings are referenced from the last valid address to the first transitioning address. 4. This parameter is sampled and not 100% tested. 5. Device is continuously selected (S VIL). 6. Addresses valid prior to or coincident with S going low.

tr = Rise Time tf = Fall Time 50% = Timing Reference Levels 0.1 µF VEE V RL


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