Details, datasheet, quote on part number: DS90C031B
PartDS90C031B
CategoryInterface and Interconnect => LVDS (Low Voltage Differential Signaling) => Line Drivers, Receivers and Transceivers
TitleLine Drivers, Receivers and Transceivers
DescriptionDS90C031B - LVDS Quad CMOS Differential Line Driver, Package: Soic Narrow, Pin Nb=16
CompanyNational Semiconductor Corporation
DatasheetDownload DS90C031B datasheet
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Features, Applications
DS90C031B LVDS Quad CMOS Differential Line Driver

The is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. The DS90C031B accepts TTL/CMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition the driver supports a TRI-STATE function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state 11 mW typical. In addition, the DS90C031B provides power-off high impedance LVDS outputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present. The DS90C031B and companion line receiver (DS90C032B) provide a new alternative to high power pseudo-ECL devices for high speed point-to-point interface applications.

Features

> 155.5 Mbps (77.7 MHz) switching rates High impedance LVDS outputs with power-off 350 mV differential signaling Ultra low power dissipation 400 ps maximum differential skew 3.5 ns maximum propagation delay Industrial operating temperature range Pin compatible with DS26C31, MB571 (PECL) and 41LG (PECL) n Conforms to ANSI/TIA/EIA-644 LVDS standard n Offered in narrow body SOIC package n Fail-safe logic for floating inputs

Enables EN L All other combinations of ENABLE inputs EN* H Input DIN Outputs DOUT+ DOUT- H L
Maximum Junction Temperature ESD Rating (Note 7) (HBM, k, 100 pF) (EIAJ, , 200 pF)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Input Voltage (DIN) Enable Input Voltage (EN, EN*) Output Voltage (DOUT+, DOUT-) Short Circuit Duration (DOUT+, DOUT-) M Package Derate M Package Storage Temperature Range Lead Temperature Range Soldering (4 sec.) -0.3V to (VCC -0.3V to (VCC to +5.8V Continuous mW 8.5 mW/C above +150C +260C

Min Supply Voltage (VCC) +4.5 -40 Operating Free Air Temperature (TA) +85 C Typ +5.0 Max +5.5 Units V

Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 2, 3) Symbol VOD1 Parameter Differential Output Voltage Change in Magnitude of VOD1 for Complementary Output States Offset Voltage Change in Magnitude of VOS for Complementary Output States Output Voltage High Output Voltage Low Input Voltage High Input Voltage Low Input Current Input Clamp Voltage Output Short Circuit Current Output TRI-STATE Current Power - Off Leakage No Load Supply Current Drivers Enabled Loaded Supply Current Drivers Enabled No Load Supply Current Drivers Disabled VIN = VCC, GND, or 0.4V ICL -18 mA VOUT = 0V (Note = 0.8V and EN* = 2.0V, VOUT 0V or VCC or 2.4V, VCC 0V or Open DIN = VCC or GND DIN = 100 (all channels) VIN = VCC or GND (all inputs) DIN = VCC or GND EN = GND, EN* = VCC DOUT-, DOUT+ DIN, EN, EN* RL GND Conditions = 100 (Figure 1) Pin DOUT-, DOUT+ Min 250 Typ 345 4 Max 450 35 Units mV |mV|

VCC = +25C (Notes 6, 9) Symbol tPHLD tPLHD tSKD tSK1 Parameter Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Skew |tPHLD tPLHD| Channel-to-Channel Skew (Note 4) Conditions 5 pF (Figure 2 and Figure 3) Min Typ Max Units ns ps

VCC = +25C (Notes 6, 9) Symbol tTLH tTHL tPHZ tPLZ tPZH tPZL Rise Time Fall Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Parameter

VCC to +85C (Notes 6, 9) Symbol tPHLD tPLHD tSKD tSK1 tSK2 tTLH tTHL tPHZ tPLZ tPZH tPZL Parameter Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Skew |tPHLD tPLHD| Channel-to-Channel Skew (Note 4) Chip to Chip Skew (Note 5) Rise Time Fall Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low 5 pF (Figure 4 and Figure Conditions 5 pF (Figure 2 and Figure 3) Min Typ Max Units ps ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation. Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: VOD1 and VOD1. Note 3: All typicals are given for: VCC = +25C. Note 4: Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the same chip with an event on the inputs. Note 5: Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays. Note 6: Generator waveform for all tests unless otherwise specified: = 1 MHz, tr 6 ns, and tf 6 ns. Note 7: ESD Ratings: HBM k, 100 pF) 2kV EIAJ (0, 200 pF) 250V Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Note 9: CL includes probe and jig capacitance.


 

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