Details, datasheet, quote on part number: DS90C363A
PartDS90C363A
CategoryOptoelectronics => Display => LCD Display => Flat Panel
DescriptionDS90C363A - +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link - 65MHz, Package: Tssop, Pin Nb=48
CompanyNational Semiconductor Corporation
DatasheetDownload DS90C363A datasheet
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Features, Applications

+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz +3.3VLVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz

DS90C363A/DS90CF363A +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz +3.3VLVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz

The DS90C363A/DS90CF363A transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 170 Mbytes/ sec. The DS90C363A transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. The DS90CF363A is fixed as a Falling edge strobe transmitter. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF364) without any translation logic. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

Features

to 65 MHz shift clock support n Rejects 3ns Jitter from VGA chip with less than 225ps output Jitter @65MHz (TJCC) n BestinClass Set & Hold Times on TxINPUTs n Tx power consumption 130 mW (typ) @65MHz Grayscale > 50% Less Power Dissipation than BiCMOS Alternatives n Tx Power-down mode < 200W (max) n ESD rating 7 kV (HBM), > 500V (EIAJ) n Supports VGA, SVGA, XGA and Dual Pixel SXGA. n Narrow bus reduces cable size and cost to 1.3 Gbps throughput to 170 Megabytes/sec bandwidth 345 mV (typ) swing LVDS devices for low EMI n PLL requires no external components n Compatible with TIA/EIA-644 LVDS standard n Low profile 48-lead TSSOP package n Improved replacement for: SN75LVDS84 DS90CF363A

TRI-STATE is a registered trademark of National Semiconductor Corporation.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) CMOS/TTL Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration Junction Temperature Storage Temperature Lead Temperature (Soldering, 4 sec) MTD48 (TSSOP) Package: -0.3V to (VCC -0.3V to (VCC + 0.3V) Continuous +150C +260C

Min Nom Max Supply Voltage (VCC) Operating Free Air Temperature (TA) Receiver Input Range Supply Noise Voltage (VCC) TxCLKIN frequency C V mVPP MHz 3.3 3.6 Units V

Over recommended operating supply and temperature ranges unless otherwise specified. Symbol VIH VIL VCL IIN Parameter High Level Input Voltage Low Level Input Voltage Input Clamp Voltage Input Current ICL mA V LVDS DC SPECIFICATIONS VOD VOS IOS IOZ Differential Output Voltage Change in VOD between complimentary output states Offset Voltage (Note 4) Change in VOS between complimentary output states Output Short Circuit Current Output TRI-STATE Current VOUT = 100 Power Down = 0V, VOUT = 5 pF, Worst Case Pattern (Figures = 5 pF, 16 Grayscale Pattern (Figures 2, 32.5 MHz = 37.5 MHz = 65 MHz = 32.5 MHz = 37.5 MHz = 65 MHz mA A

TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current Worst Case mA A
Power Down = Low Driver Outputs in TRI-STATE under Power Down Mode

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation. Note 2: Typical values are given for VCC = 3.3V and = +25C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and VOD Note 4: VOS previously referred as VCM.

Over recommended operating supply and temperature ranges unless otherwise specified Symbol TCIT TCIP TCIH TCIL TxCLK IN Period (Figure 6 ) TxCLK IN High Time (Figure 6 ) TxCLK IN Low Time (Figure 6 ) Parameter TxCLK IN Transition Time (Figure T 0.5T Min Typ Max 55.6 0.65T Units ns

Over recommended operating supply and temperature ranges unless otherwise specified Symbol LLHT LHLT TPPos5 TPPos6 TSTC THTC TCCD TJCC Parameter LVDS Low-to-High Transition Time (Figure 4 ) LVDS High-to-Low Transition Time (Figure 4 ) Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5) Transmitter Output Pulse Position for Bit 1 Transmitter Output Pulse Position for Bit 2 Transmitter Output Pulse Position for Bit 3 Transmitter Output Pulse Position for Bit 4 Transmitter Output Pulse Position for Bit 5 Transmitter Output Pulse Position for Bit 6 Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5) Transmitter Output Pulse Position for Bit 1 Transmitter Output Pulse Position for Bit 2 Transmitter Output Pulse Position for Bit 3 Transmitter Output Pulse Position for Bit 4 Transmitter Output Pulse Position for Bit 5 Transmitter Output Pulse Position for Bit 6 Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5) Transmitter Output Pulse Position for Bit 1 Transmitter Output Pulse Position for Bit 2 Transmitter Output Pulse Position for Bit 3 Transmitter Output Pulse Position for Bit 4 Transmitter Output Pulse Position for Bit 5 Transmitter Output Pulse Position for Bit 6 TxIN Setup to TxCLK IN (Figure 6 ) TxIN Hold to TxCLK IN (Figure 6 ) TxCLK IN to TxCLK OUT Delay (Figure A=25C, VCC=3.3V TxCLK IN to TxCLK OUT Delay (Figure 7 ) Transmitter Jitter Cycle-to-Cycle (Figures 13 ) (Note = 65 MHz = 40 MHz = 32.5 MHz TPLLS TPDD Transmitter Phase Lock Loop Set (Figure 8 ) Transmitter Power Down Delay (Figure = 32.5 MHz = 40 MHz = 65 MHz Min Typ Max Units ms ns

Note 5: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This parameter is functionality tested only on Automatic Test Equipment (ATE). Note 6: The Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. Output jitter is measured with a cycle-to-cycle jitter of 3ns applied to the input clock signal. A jitter event of 3ns, represents worse case jump in the clock edge from most Graphics controller VGA chips currently available. This parameter is used when calculating system margin (RSKM). See Figures 12, 13 and AN-1059.


 

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