Details, datasheet, quote on part number: DS90C383MTD
PartDS90C383MTD
CategoryOptoelectronics => Display => LCD Display => Flat Panel
DescriptionDS90CF384 - +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 Mhz, Package: Tssop, Pin Nb=56
CompanyNational Semiconductor Corporation
DatasheetDownload DS90C383MTD datasheet
Cross ref.Similar parts: DS90C383BMT/NOPB, SN75LVDS83BDGG, DS90CF383B, SN65LVDS93A, SN75LVDS83A, SN75LVDS83C, DS90CR285, DS90CR287, SN65LVDS93, SN65LVDS93A-Q1
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Features, Applications
DS90C383/DS90CF384 +3.3V Programmable LVDS 24-Bit-Color Flat Panel Display (FPD) Link--65 MHz

DS90C383/DS90CF384 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link--65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link--65 MHz

The DS90C383 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CF384 receiver converts the LVDS data streams back into 28 bits of LVCMOS/ LVTTL data. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 227 Mbytes/sec. The transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphics controllers. The transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge transmitter will inter-operate with a Falling edge receiver (DS90CF384) without any translation logic. Both devices are also offered a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which provides 44 % reduction in PCB footprint compared to the TSSOP package. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

Features

to 65 MHz shift clock support n Programmable transmitter (DS90C383) strobe select (Rising or Falling edge strobe) n Single 3.3V supply n Chipset (Tx + Rx) power consumption 250 mW (typ) n Power-down mode 0.5 mW total) n Single pixel per clock XGA (1024x768) ready n Supports VGA, SVGA, XGA and higher addressability. to 227 Megabytes/sec bandwidth to 1.8 Gbps throughput n Narrow bus reduces cable size and cost 290 mV swing LVDS devices for low EMI n PLL requires no external components n Low profile 56-lead TSSOP package. n Also available a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package n Falling edge data strobe Receiver n Compatible with TIA/EIA-644 LVDS standard n ESD rating kV n Operating Temperature: to +85C

TRI-STATE is a registered trademark of National Semiconductor Corporation.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) to +4V CMOS/TTL Input Voltage -0.3V to (VCC + 0.3V) CMOS/TTL Output Voltage -0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage -0.3V to (VCC + 0.3V) LVDS Driver Output Voltage -0.3V to (VCC + 0.3V) LVDS Output Short Circuit Duration Continuous Junction Temperature +150C Storage Temperature to +150C Lead Temperature (Soldering, 4 sec for TSSOP) +260C Solder Reflow Temperature (20 sec for FBGA) +220C Maximum Package Power Dissipation Capacity 25C MTD56 (TSSOP) Package: 1.61 W Package Derating: DS90C383MTD 12.5 mW/C above +25C

DS90CF384MTD 12.4 mW/C above Maximum Package Power Dissipation Capacity 25C SLC64A Package: DS90C383SLC DS90CF384SLC Package Derating: DS90C383SLC 10.2 mW/C above DS90CF384SLC 10.2 mW/C above ESD Rating (HBM, k, 100 pF)

Supply Voltage (VCC) Operating Free Air Temperature (TA) Receiver Input Range Supply Noise Voltage (VCC) Min -40 0 Nom 3.3 +25 Max Units C V mVPP

Over recommended operating supply and temperature ranges unless otherwise specified. Symbol VIH VIL VOH VOL VCL IIN IOS VOD VOS IOS IOZ VTH VTL IIN Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Clamp Voltage Input Current Output Short Circuit Current Differential Output Voltage Change in VOD between complimentary output states Offset Voltage (Note 4) Change in VOS between complimentary output states Output Short Circuit Current Output TRI-STATE Current Differential Input High Threshold Differential Input Low Threshold Input Current VIN = +2.4V, VCC = 3.6V VIN = 0V, VCC = 3.6V TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current Worst Case = 5 pF, Worst Case Pattern = 32.5 MHz = 37.5 MHz mA VOUT = 100 Power Down = 0V, VOUT 0V or VCC VCM V mV IOH -0.4 mA IOL 2 mA ICL -18 mA VIN = VCC, GND, or 0.4V VOUT 100 250 Conditions Min 2.0 GND Typ Max VCC 0.8 Units mA mV LVCMOS/LVTTL DC SPECIFICATIONS


 

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