Details, datasheet, quote on part number: MC-4532DA726EFB-A10
PartMC-4532DA726EFB-A10
CategoryAnalog & Mixed-Signal Processing
Description32 M-word BY 72-bit Synchronous Dynamic RAM Module Registered Type
CompanyNEC Electronics Inc.
DatasheetDownload MC-4532DA726EFB-A10 datasheet
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Features, Applications

32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE
Description

The a 33,554,432 words by 72 bits synchronous dynamic RAM module on which 18 pieces of 128M SDRAM: µPD45128441 are assembled. These modules provide high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction.

Features
33,554,432 words by 72 bits organization (ECC type) Clock frequency and access time from CLK

Part number /CAS latency Clock frequency (MAX.) 2 125 MHz 100 MHz 100 MHz 77 MHz 125 MHz 100 MHz 100 MHz 77 MHz Access time from CLK (MAX.) ns PC100 Registered DIMM Rev. 1.2 Compliant Module type

Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge Pulsed interface Possible to assert random column address in every cycle Quad internal banks controlled by BA0 and BA1 (Bank Select) Programmable burst-length and Full Page) Programmable wrap sequence (Sequential / Interleave) Programmable /CAS latency (2, 3) Automatic precharge and controlled precharge CBR (Auto) refresh and self refresh All DQs have of series resistor Single 0.3 V power supply LVTTL compatible 4,096 refresh cycles / 64 ms Burst termination by Burst Stop command and Precharge command 168-pin dual in-line memory module (Pin pitch = 1.27 mm) Registered type Serial PD

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. M13633EJ7V0DS00 (7th edition) Date Published February 2000 NS CP(K) Printed in Japan
Part number Clock frequency (MAX.) 125 MHz 100 MHz 125 MHz 100 MHz Package Mounted devices

168-pin Dual In-line Memory Module 18 pieces of µPD45128441G5 (Rev. E) (Socket Type) Edge connector: Gold plated 43.18 mm height mm (400) TSOP (II)) 18 pieces of µPD45128441G5 (Rev. mm (400) TSOP (II))

168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)

: Address Inputs : SDRAM Bank Select : Clock Input : Clock Enable Input : Write Protect : Chip Select Input : Row Address Strobe : Column Address Strobe : Write Enable : DQ Mask Enable : Address Input for EEPROM : Serial Data I/O for PD : Clock Input for PD : Power Supply : Ground : Register / Buffer Enable : No Connection


 

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